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Full_Adder_Gate_Level - EDA Playground

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testbench.sv

 
// Testbench for Full_Adder
​
`timescale 1ns/1ns
​
module Test_Full_Adder; // No need for Ports
​
  reg  a, b, c;    // variables
  wire sum, cout;  // wires
​
  // Instantiate the module to be tested
  Full_Adder FA (a, b, c, cout, sum);
​
  initial begin    // initial block
    $dumpfile("Test_Full_Adder.vcd");
    $dumpvars(1, FA);
    a=0; b=0; c=0; // at t=0 time units
    #20 a=1; b=1;  // at t=20
    #20 a=0; b=0; c=1; // at t=40
    #20 a=1; c=0; // at t=60
    #20 $finish;    // at t=80 finish simulation
​
  end   // end of initial block
endmodule
​

design.sv

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`timescale 1ns/1ns
​
module Full_Adder(input a, b, c, output cout, sum);
  wire w1, w2, w3; 
  and #2 (w1, a, b);
  xor #3 (w2, a, b);
  and #2 (w3, w2, c);
  xor #3 (sum, w2, c);
  or  #2 (cout, w1, w3);
endmodule
​

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