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// Code your testbench here
// or browse Examples
`include "uvm_macros.svh"
import uvm_pkg::*;
`include "seq_item.sv"
class base_seq extends uvm_sequence #(seq_item);
seq_item req;
uvm_phase phase;
`uvm_object_utils(base_seq)
function new (string name = "base_seq");
super.new(name);
endfunction
task pre_body();
`uvm_info(get_type_name(), "Inside pre_body", UVM_LOW);
endtask
task body();
`uvm_info(get_type_name(), "Base seq: Body started", UVM_LOW);
req = seq_item::type_id::create("req");
// send to the driver
#20;
`uvm_info(get_type_name(), "Base seq: Body completed", UVM_LOW);
endtask
task post_body();
`uvm_info(get_type_name(), "Inside post_body", UVM_LOW);
endtask
endclass
class base_test extends uvm_test;
base_seq bseq;
`uvm_component_utils(base_test)
function new(string name = "base_test", uvm_component parent = null);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
bseq = base_seq::type_id::create("bseq");
bseq.set_starting_phase(phase);
bseq.set_automatic_phase_objection(1);
bseq.start(null);
endtask
endclass
module tb_top;
initial begin
run_test("base_test");
end
endmodule
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class seq_item extends uvm_sequence_item;
rand bit[15:0] addr;
rand bit[15:0] data;
`uvm_object_utils(seq_item)
function new(string name = "seq_item");
super.new(name);
endfunction
endclass
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// Code your design here
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