Verification Practice - CPU - POR - EDA Playground
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package cpu_rtl_pkg;
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// opcodes
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typedef enum logic [2:0] {HLT, SKZ, ADD, AND, XOR, LDA, STO, JMP} opcode_t;
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// sequential states of controller state machine
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typedef enum {INST_ADDR, INST_FETCH, INST_LOAD, IDLE, OP_ADDR, OP_FETCH, ALU_OP, STORE} state_t;
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​
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endpackage : cpu_rtl_pkg
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///////////////////////////////////////////////////////////////////////////
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// (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved.
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//
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// File name   : control.sv
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// Title       : Control Module
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// Project     : SystemVerilog Training
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// Created     : 2013-4-8
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// Description : Defines the Control module
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// Notes       :
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//
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///////////////////////////////////////////////////////////////////////////
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​
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// SystemVerilog package for opcode_t and state_t
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import cpu_rtl_pkg::*;
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​
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module control  (
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                output logic      load_ac ,
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                output logic      mem_rd  ,
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                output logic      mem_wr  ,
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                output logic      inc_pc  ,
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                output logic      load_pc ,
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                output logic      load_ir ,
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                output logic      halt    ,
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                input  opcode_t opcode  ,
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                input             zero    ,
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                input             clk     ,
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                input             rst_  
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                );
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// SystemVerilog: time units and time precision specification
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timeunit 1ns;
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timeprecision 100ps;
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​
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state_t state;
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​
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logic aluop;
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​
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assign aluop = (opcode inside {ADD, AND, XOR, LDA});
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​
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always_ff @(posedge clk or negedge rst_)
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  if (!rst_)
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     state <= INST_ADDR;
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  else
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     state <= state.next();
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​
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always_comb  begin
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  {mem_rd, load_ir, halt, inc_pc, load_ac, load_pc, mem_wr}  =  7'b000_0000;
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  unique case (state)
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    INST_ADDR : ;
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    INST_FETCH: mem_rd = 1;  
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    INST_LOAD : begin        
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                mem_rd = 1;  
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                load_ir = 1;
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                end
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    IDLE      : begin
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                mem_rd = 1;
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                load_ir = 1;
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                end
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    OP_ADDR   : begin      
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                inc_pc = 1;
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                halt = (opcode == HLT);
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                end
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    OP_FETCH  : mem_rd = aluop;
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    ALU_OP    : begin        
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                load_ac = aluop;
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                mem_rd = aluop;
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                inc_pc = ((opcode == SKZ) && zero);
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                load_pc = ( opcode == JMP);
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                end
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    STORE     : begin
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                load_ac = aluop;
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                mem_rd = aluop;
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                inc_pc = (opcode == JMP);
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                load_pc = ( opcode == JMP);
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                mem_wr = ( opcode == STO);
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                end
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  endcase
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  end
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​
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endmodule
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Verification Practice - CPU - POR
​
Notes:
-An EDA Playground bug may require untoggling the "Show output file after run" radio button under "Run Options".
-EDA Playground is great, but can be glitchy and laggy. Sim last confirmed functional June 21, 2023.
-CPU test details: Binary loaded into memory from cpu_testbench_top.sv ($readmemb), prior to test start.  A test is run without stimulus (already loaded in memory), and an objection in the scoreboard is dropped when the CPU has reached a designated 'success address'. The assumption is that if the CPU is not working properly, it will not reach the 'success address'.
-I produced the testbench (and improved it with feedback from others!), but the CPU RTL is from a Cadence training course.
-Block level testbenches linked on project github page, below.
​
​
Project summary: 
https://github.com/taylortempleton/VerificationPractice_SimpleCPU

Verification Practice - CPU - POR

Notes:
-An EDA Playground bug may require untoggling the "Show output file after run" radio button under "Run Options".
-EDA Playground is great, but can be glitchy and laggy. Sim last confirmed functional June 21, 2023.
-CPU test details: Binary loaded into memory from cpu_testbench_top.sv ($readmemb), prior to test start. A test is run without stimulus (already loaded in memory), and an objection in the scoreboard is dropped when the CPU has reached a designated 'success address'. The assumption is that if the CPU is not working properly, it will not reach the 'success address'.
-I produced the testbench (and improved it with feedback from others!), but the CPU RTL is from a Cadence training course.
-Block level testbenches linked on project github page, below.

Project summary:
https://github.com/taylortempleton/VerificationPractice_SimpleCPU

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