UVM TestBench Example code - verificationguide.com - EDA Playground
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//-------------------------------------------------------------------------
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//              www.verificationguide.com   testbench.sv
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//-------------------------------------------------------------------------
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//---------------------------------------------------------------
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//including interfcae and testcase files
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`include "mem_interface.sv"
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`include "mem_test.sv"
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`include "mem_wr_rd_test.sv"
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//---------------------------------------------------------------
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​
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module tbench_top;
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​
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  //---------------------------------------
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  //clock and reset signal declaration
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  //---------------------------------------
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  bit clk;
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  bit reset;
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  //---------------------------------------
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  //clock generation
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  //---------------------------------------
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  always #5 clk = ~clk;
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  //---------------------------------------
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  //reset Generation
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  //---------------------------------------
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  initial begin
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    reset = 1;
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    #5 reset =0;
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  end
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  //---------------------------------------
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  //interface instance
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  //---------------------------------------
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  mem_if intf(clk,reset);
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  //---------------------------------------
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  //DUT instance
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  //---------------------------------------
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  memory DUT (
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    .clk(intf.clk),
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    .reset(intf.reset),
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    .addr(intf.addr),
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    .wr_en(intf.wr_en),
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    .rd_en(intf.rd_en),
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    .wdata(intf.wdata),
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    .rdata(intf.rdata)
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   );
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  //---------------------------------------
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  //passing the interface handle to lower heirarchy using set method
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  //and enabling the wave dump
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  //---------------------------------------
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  initial begin
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    uvm_config_db#(virtual mem_if)::set(uvm_root::get(),"*","vif",intf);
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    //enable wave dump
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    $dumpfile("dump.vcd");
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    $dumpvars;
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  end
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  //---------------------------------------
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  //calling test
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  //---------------------------------------
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  initial begin
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    run_test();
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  end
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endmodule
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//-------------------------------------------------------------------------
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//              Memory Model RTL - www.verificationguide.com
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//-------------------------------------------------------------------------
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/*
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              -----------------
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              |               |
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    addr ---->|               |
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              |               |------> rdata
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              | Memory Model  |
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   wdata ---->|               |
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              |               |
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              -----------------
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                   ^     ^
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                   |     |
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                wr_en  rd_en
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​
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-------------------------------------------------------------------------- */
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module memory
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  #( parameter ADDR_WIDTH = 2,
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     parameter DATA_WIDTH = 8 ) (
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    input clk,
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    input reset,
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    //control signals
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    input [ADDR_WIDTH-1:0]  addr,
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    input                   wr_en,
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    input                   rd_en,
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    //data signals
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    input  [DATA_WIDTH-1:0] wdata,
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    output [DATA_WIDTH-1:0] rdata
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  );
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  reg [DATA_WIDTH-1:0] rdata;
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  //Memory
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  reg [DATA_WIDTH-1:0] mem [2**ADDR_WIDTH];
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​
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  //Reset
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  always @(posedge reset)
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    for(int i=0;i<2**ADDR_WIDTH;i++) mem[i]=8'hFF;
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  // Write data to Memory
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  always @(posedge clk)
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    if (wr_en)    mem[addr] <= wdata;
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​
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  // Read data from memory
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  always @(posedge clk)
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    if (rd_en) rdata <= mem[addr];
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​
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endmodule
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UVM TestBench Example code. www.verificationguide.com

UVM TestBench Example code. www.verificationguide.com

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