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/*
Author: Sujeet Kumar Layek
Designation: IP/SoC Verification Engineer
*/
import uvm_pkg::*;
`include "uvm_macros.svh"
// TOP
module top;
int a = 5;
;
initial
begin
// Setting the value of the variable for lower hierarchy
uvm_config_db #(int) :: set (null,"*","inttt",a);
// Calling the 'test' from top.
run_test();
end
endmodule
// SEQUENCER
class seqr extends uvm_sequencer;
`uvm_sequencer_utils(seqr)
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction
endclass
// SEQUENCE
class seq extends uvm_sequence;
`uvm_object_utils (seq)
int d = 10; // This 'd' will take the value of 'a' which has been set in top.
function new(string name = "seq");
super.new(name);
endfunction
virtual task body();
$display("get_full_name:");
`uvm_info (get_full_name(), $sformatf (" :: Set the local value of 'SEQ' D = %0d\n", d), UVM_LOW )
$display("get_type_name:");
`uvm_info (get_type_name(), $sformatf (" :: Set the local value of 'SEQ' D = %0d\n", d), UVM_LOW )
$display("get_name:");
`uvm_info (get_name(), $sformatf (" :: Set the local value of 'SEQ' D = %0d\n", d), UVM_LOW )
uvm_config_db #(int) :: get (null, get_full_name(),"inttt", d);
$display("\n************************************");
$display("Class 'SEQ' get from top :: D = %0d",d);
$display("************************************\n");
endtask
endclass
// ENV
class env extends uvm_component;
`uvm_component_utils(env)
int c;
seqr seqr_h;
function new(string name = "env", uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase (uvm_phase phase);
// Creating 'SEQUENCER' inside 'ENV'
seqr_h = seqr::type_id::create("seqr_h",this);
// Getting the value of the variable in ENV in a different variable
uvm_config_db #(int) :: get (this,"","int",c);
$display("\n************************************");
$display("Class 'ENV' get from top :: C = %0d",c);
$display("************************************\n");
endfunction
endclass
// TEST
class test extends uvm_component;
`uvm_component_utils(test)
int b;
env env_h;
seq seq_h;
function new(string name = "test", uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase (uvm_phase phase);
// Creating 'ENV' inside 'TEST'
env_h = env::type_id::create("env_h",this);
// Getting the value of the variable in TEST in a different variable
uvm_config_db #(int) :: get (this,"","int",b);
$display("\n************************************");
$display("Class 'TEST' get from top :: B = %0d",b);
$display("************************************\n");
endfunction
virtual function void end_of_elaboration_phase (uvm_phase phase);
$display ("\nPrinting the UVM Topology: -\n");
uvm_top.print_topology ();
endfunction
// Start the sequence
virtual task run_phase(uvm_phase phase);
// Creating 'SEQ' inside 'TEST'
seq_h = seq::type_id::create("seq_h");
// UVM Objection
phase.raise_objection(this);
seq_h.start (env_h.seqr_h);
phase.drop_objection(this);
endtask
endclass
xxxxxxxxxx
// Code your design here
/*
Differences between
get_full_name,
get_type_name and
get_name
in UVM.
get_full_name():
It will show the complete hierarchical path starting from tb_top.test.env..
and so on till your object type in the output log file.
get_type_name():
It will return only the "class name" irrespective of hierarchy.
get_name():
It will return the "handle name" you have defined for the same class where
it has been used.
*/
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