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// Code your testbench here
// or browse Examples
module top;
  bit clk,reset;
  bit sig1,sig2,sig3;
  int data_load=0;
  always #5 clk=!clk; 
 
  // If new sig1 then data_load will be stable starting from the next clock 
  // until sig2. At sig2 data_load is changed in value and in the next cycle sig3==1
  /*property p_with_sig2;
    int v; 
    @(posedge clk) disable iff(reset)
    ($rose(sig1), v=data_load) |-> ##1 first_match(data_load==v[*1:$] ##1 sig2) 
                                  ##0 data_load !=v ##1 sig3;
  endproperty
  ap_with_sig2: assert property (p_with_sig2);*/
 
  //  if data_load changes between Sig1 and Sig2 posedges,
  // then Sig3 must get asserted within let's say 1 to 10 clocks
  property p_with_no_sig2;
    int v; 
    @(posedge clk) disable iff(reset)
    ($rose(sig1), v=data_load) ##1 (data_load!=v && !sig2)[->1] |-> ##[1:30] sig3;
  endproperty
  ap_with_no_sig2: assert property (p_with_no_sig2);
 
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0);
    #200 $finish;
  end
    
  initial begin
    fork 
       
       #10 sig1<=1;  
       #25 sig2<=1;
       #20 data_load<=10;
      // #26 sig3<=1; 
    join
    
  end
 
    endmodule
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