Contador 3 bits - EDA Playground
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library IEEE;
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use IEEE.std_logic_1164.all;
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​
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entity TB_cont_3_bits is
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end;
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​
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​
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​
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architecture beh of TB_cont_3_bits is
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​
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    signal clk,rst : std_logic:='0';
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    signal Q2,Q1,Q0: std_logic;
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    component cont_3_bits is
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        port(   clk: in std_logic;
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            rst: in std_logic;
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            Q2: out std_logic;
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            Q1: out std_logic;
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            Q0: out std_logic);
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    end component;
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​
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begin
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    DUT: cont_3_bits port map (clk,rst,Q2,Q1,Q0);
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    clk <= not clk after 10 ns;
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​
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    rst <= '0','1' after 5 ns,'0' after 45 ns, '1' after 215 ns, '0' after 235 ns;
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    end;
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​
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library IEEE;
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use IEEE.std_logic_1164.all;
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​
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entity cont_3_bits is
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    port(   clk: in std_logic;
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        rst: in std_logic;
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        Q2: out std_logic;
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        Q1: out std_logic;
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        Q0: out std_logic);
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end;
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​
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architecture beh of cont_3_bits is
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    signal D2,D1,D0 : std_logic;
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    signal Q2_aux,Q1_aux,Q0_aux : std_logic;
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    component FF_D is
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        port(   D: in std_logic;
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            clk: in std_logic;
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            rst: in std_logic;
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            Q: out std_logic);
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    end component;
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begin
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    D2 <= (Q2_aux and not Q1_aux) or (not Q2_aux and Q1_aux and Q0_aux) or(Q2_aux and not Q0_aux);
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    D1 <= Q1_aux xor Q0_aux;
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    D0 <= not Q0_aux;
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    FF2: FF_D port map (D2,clk,rst,Q2_aux);
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    FF1: FF_D port map (D1,clk,rst,Q1_aux);
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    FF0: FF_D port map (D0,clk,rst,Q0_aux);
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    Q2<= Q2_aux;
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    Q1<= Q1_aux;
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    Q0<= Q0_aux;
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end;
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​
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