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//UVM package

`include "uvm_macros.svh"

import uvm_pkg::*;

​

//`include "files.svh"

​

//Files

`include "interface.svh"

`include "sequence_item.svh"

`include "sequence.svh"

`include "sequencer.svh"

`include "monitor.svh"

`include "driver.svh"

`include "agent.svh"

`include "scoreboard.svh"

`include "env.svh"

`include "test.svh"

​

//Declaration

module dff_top_tb;

  logic clk;

//Instantiate 

  dff_interf intf(.clk(clk));

​

// Connect the DUT 

  dff dut_inst (

    .clk (intf.clk),

    .rst (intf.rst),

    .din (intf.din),

    .dout(intf.dout)

  );

​

//Connecting virtual interface 

  initial begin

    //driver -- set here, get in driver file

    uvm_config_db#(virtual dff_interf)::set(null, "uvm_test_top.env.agent.driver", "vif", intf);

​

    //monitor -- set here, get in monitor file

    uvm_config_db#(virtual dff_interf)::set(null, "uvm_test_top.env.agent.monitor", "vif", intf);

  end

​

  // Clk generation

  always #10 clk = ~clk;

​

  //  Stimulation block

  initial begin

    clk = 1;

    intf.rst = 1;

    intf.din = 1;

    #10 intf.rst = 0;

    repeat (10) begin

      #10 intf.din = $urandom % 2; 

      `uvm_info("top", $sformatf("clk = %b, rst = %b, din = %b, dout = %b", clk, intf.rst, intf.din, intf.dout), UVM_MEDIUM)

    end

  end

​

​

  // Display 

//  initial begin

//    $monitor($time, " clk = %b, rst = %b, din = %b, dout = %b", clk, intf.rst, intf.din, intf.dout);

//  end

​

  // Run UVM test

  initial begin 

    run_test("dff_test");

  end

​

  // Dump waveform

  initial begin 

    $dumpfile("dump.vcd");

    $dumpvars();

  end

endmodule

​

class dff_seq_item extends uvm_sequence_item; 

  // UVM factory reg 

  `uvm_object_utils(dff_seq_item)

  rand logic rst;

  rand logic din;

  rand logic dout;

  //default constructor 

  function new(string name = "dff_seq_item");

    super.new(name);

    `uvm_info("sequence item class", "constructor", UVM_HIGH)

  endfunction

​

  constraint wr_rd_c { rst != 1; }; 

endclass

interface dff_interf(input logic clk) ; 

  //signals

  logic rst;

  logic din;

  logic dout;

endinterface

import uvm_pkg::*;

​

class dff_seq extends uvm_sequence #(dff_seq_item);

  // UVM factory registration

  `uvm_object_utils(dff_seq)

  dff_seq_item tx;

  // Default constructor

  function new(string name = "dff_seq");

    super.new(name);

    `uvm_info("sequence Class", "constructor", UVM_NONE)

  endfunction

​

  task body();

    repeat(5) begin

      tx = dff_seq_item::type_id::create("tx", null);

      wait_for_grant();

      assert(tx.randomize()) else `uvm_error("SEQ", "Randomization failed");

      send_request(tx);

      wait_for_item_done();

    end

  endtask

endclass

​

class dff_seqr extends uvm_sequencer#(dff_seq_item);

  `uvm_component_utils(dff_seqr)// UVM factory reg

  //Default constructor

  function new(string name = "dff_sequencer",uvm_component parent);

    super.new(name,parent);

    `uvm_info("sequencer Class","constructor",UVM_NONE)

  endfunction

endclass

class dff_monitor extends uvm_monitor;

  // UVM factory reg

  `uvm_component_utils(dff_monitor)

  virtual dff_interf intf;

  uvm_analysis_port #(dff_seq_item) item_collected_port;

  dff_seq_item tx;

​

   //Default constructor

  function new(string name = "dff_monitor",uvm_component parent);

     super.new(name,parent);

     `uvm_info("monitor class", "constructor", UVM_NONE)

  endfunction

  //Build phase

  function void build_phase(uvm_phase phase);

      super.build_phase(phase);

           item_collected_port = new("item_collected_port", this);

    // virtual interface

    if(!uvm_config_db#(virtual dff_interf   )::get(this, "", "vif", intf))

      `uvm_fatal("no_inif in driver","virtual interface get failed from config db");

  endfunction

  task run_phase(uvm_phase phase);

    tx = dff_seq_item::type_id::create("tx");

    wait(!intf.rst)

    @(posedge intf.clk)

    tx.rst = logic'(intf.rst); 

    tx.din = intf.din;

    tx.dout = intf.dout;

​

    item_collected_port.write(tx); 

  endtask

​

endclass

class dff_agent extends uvm_agent;

  // UVM factory reg

  `uvm_component_utils(dff_agent)

  // Declaration

  dff_driver driver;

  dff_seqr seqr;

  dff_monitor monitor;

  // Default constructor 

  function new(string name = "dff_agent", uvm_component parent);

    super.new(name, parent);

    `uvm_info("Agent Class", "Constructor", UVM_NONE);

  endfunction

  // Build phase

  function void build_phase(uvm_phase phase);

    super.build_phase(phase);

    driver  = dff_driver::type_id::create("driver", this);

    seqr    = dff_seqr::type_id::create("sequencer", this);

    monitor = dff_monitor::type_id::create("monitor", this);

  endfunction

  // Connect phase

  function void connect_phase(uvm_phase phase);

    super.connect_phase(phase);

    `uvm_info("Agent Class", "Connect Phase", UVM_NONE);

    driver.seq_item_port.connect(seqr.seq_item_export);

    // Connects the sequencer to the driver

  endfunction

endclass

​

class dff_env extends uvm_env;

  // UVM factory reg

  `uvm_component_utils(dff_env)

  // Declarations

  dff_scoreboard scoreboard;

  dff_agent agent;

​

  // Default constructor

  function new(string name = "env", uvm_component parent);

    super.new(name, parent);

    `uvm_info("Environment Class", "Constructor", UVM_NONE)

  endfunction

​

  // Build phase

  function void build_phase(uvm_phase phase);

    super.build_phase(phase);

    scoreboard = dff_scoreboard::type_id::create("scoreboard", this);

    agent = dff_agent::type_id::create("agent", this);

  endfunction

​

  // Connect phase

  function void connect_phase(uvm_phase phase);

    super.connect_phase(phase);

    agent.monitor.item_collected_port.connect(scoreboard.item_collected_export);

  endfunction

endclass

​

​

class dff_test extends uvm_test;

  // UVM factory reg

  `uvm_component_utils(dff_test);

  //Declaration

  dff_env env;

  dff_seq seq;

  //Default constructor

  function new(string name = "test",uvm_component parent);

    super.new(name,parent);

    `uvm_info("test class","constructor",UVM_NONE);

  endfunction

  //build phase

  function void build_phase(uvm_phase phase);

    super.build_phase(phase);

    env = dff_env::type_id::create("env",this);

    seq = dff_seq::type_id::create("seq",this);

  endfunction

  //connect phase

  function void connect_phase(uvm_phase phase);

    super.connect_phase(phase);

  endfunction 

  //end_of_elaboration phase

  virtual function void end_of_elaboration();

    `uvm_info("test","constructor",UVM_NONE);

    print();

  endfunction

  //run phase

  task run_phase(uvm_phase phase);

    phase.raise_objection(this);

    seq.start(env.agent.seqr);

    phase.drop_objection(this);

  endtask

endclass

​

class dff_scoreboard extends uvm_scoreboard;

  // UVM factory reg

  `uvm_component_utils(dff_scoreboard);

  uvm_analysis_imp#(dff_seq_item,dff_scoreboard) item_collected_export;

  dff_seq_item tx_q[$];

  //constructor

  function new(string name="scoreboard",uvm_component parent);

    super.new(name,parent);

    `uvm_info("scoreboard class","constructor",UVM_NONE)

  endfunction

  //build phase

  function void build_phase(uvm_phase phase);

    super.build_phase(phase);

    item_collected_export=new("item_collected_export",this);

  endfunction

  //virtual function

  virtual function void write(dff_seq_item tx);

    $display("Pkt received");

    tx_q.push_back(tx);

  endfunction

endclass

/*`include"interface.svh"

`include"sequence_item.svh"

`include"sequence.svh"

`include"sequencer.svh"

`include"monitor.svh"

`include"driver.svh"

`include"agent.svh"

`include"scoreboard.svh"

`include"env.svh"

`include"test.svh"

*/