Code16 Inter and Intra assignment Delay.v

Code16 Inter and Intra assignment Delay.v - EDA Playground

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testbench.sv

 
module tb();
 
reg a,b;
  
///Inter assg delay
  
  /* So when you use delay on LHS, so they are termed as an inter assignment delay.*/
  
  initial begin
   #5 a <= 1'b1; 
  end
 
///Intra assg delay
  
  /* So when you use delay on RHS, so they are termed as an intera assignment delay.*/
​
  initial begin
  b <= #10 a;
  end
  
  initial begin
    $monitor("Value of a: %0b and b : %0b at time : %0t",a,b,$time);
  end
 
endmodule
​

design.sv

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OVL
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SVAUnit 3.0
ClueLib 0.6.1
svlib 0.5

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SystemC 2.3.3