VHDL-2008 Dictionary - EDA Playground
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92
 
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library ieee;
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  use ieee.std_logic_1164.all;
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​
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​
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​
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package DictP is
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​
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​
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  generic (type G_KEY_TYPE;
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           type G_DATA_TYPE);
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​
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  -- public interface
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  type t_dict is protected
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​
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    procedure set  (key : in G_KEY_TYPE; data : in G_DATA_TYPE);
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    procedure get  (key : in G_KEY_TYPE; data : out G_DATA_TYPE; err : out boolean);
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​
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  end protected t_dict;
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​
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​
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end package DictP;
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​
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​
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​
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package body DictP is
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​
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​
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  type t_dict is protected body
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​
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​
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    -- private types
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    type t_key;
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    type t_key_ptr is access t_key;
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​
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    type t_key is record
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      key        : G_KEY_TYPE;
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      data       : G_DATA_TYPE;
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      last_entry : t_key_ptr;
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      next_entry : t_key_ptr;
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    end record t_key;
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​
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    -- private properties
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    variable v_head    : t_key_ptr := null;
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​
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    -- private method
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    impure function find (key : G_KEY_TYPE) return t_key_ptr;
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​
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    -- Add a given key to given data in the dictionary
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    procedure set (key : in G_KEY_TYPE; data : in G_DATA_TYPE) is
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    begin
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      if (v_head /= null) then
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        v_head := new t_key'(key, data, v_head, null);
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        v_head.last_entry.next_entry := v_head;
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      else
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        v_head := new t_key'(key, data, null, null);  -- Here the eror occurs in ModelSim
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      end if;
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    end procedure set;
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    -- Get value of a given key from the dictionary
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    procedure get (key : in G_KEY_TYPE; data : out G_DATA_TYPE; err : out boolean) is
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      variable v_entry : t_key_ptr := null;
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    begin
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      v_entry := find(key);
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      if (v_entry /= null) then
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        data := v_entry.data;
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        err  := false;
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      else
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        err := true;
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      end if;
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    end procedure get;
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    -- Find a given key in the dict (internal method)
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    impure function find (key : G_KEY_TYPE) return t_key_ptr is
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      variable v_entry : t_key_ptr := v_head;
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    begin
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      while (v_entry /= null) loop
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        if (v_entry.key = key) then
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          return v_entry;
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        end if;
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        if (v_entry.last_entry = null) then
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          return null;
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        else
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          v_entry := v_entry.last_entry;
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        end if;
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      end loop;
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      return null;
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    end function find;
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​
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  end protected body t_dict;
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​
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end package body DictP;
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​
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-- Code your design here
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library IEEE;
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use IEEE.std_logic_1164.all;
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​
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​
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entity dummy is
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end entity dummy;
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​
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​
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architecture sim of dummy is
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begin
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end architecture sim;
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​
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Test case for potentially bug in ModelSim.

Test case for potentially bug in ModelSim.

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