LAB2: 4 to 1 Multiplexer using 2to1 Mux

testbench.sv

 
module tb_MUX4;
// Declare variables to be connected to inputs as regs
 // declared as regs since we want to change them
reg IN0, IN1, IN2, IN3;
reg S1, S0;
  
// Declare output wires since we are not changing them but only observing them
wire OUTPUT;
  
// Instantiate the multiplexer, tie the ports
  MUX4 mymux1 (
    .f(OUTPUT), 
    .w0(IN0), 
    .w1(IN1), 
    .w2(IN2), 
    .w3(IN3), 
    .s1(S1), 
    .s0(S0)) ;
 
// Stimulate the inputs, set input lines of mux and 
initial 
begin
  IN0=1; IN1=0; IN2=1; IN3=0; // you may change them as you like
 
  for(int i=0; i<4; i=i+1 ) // checking all possible values of S1,S0
    begin
      #5 {S1, S0}=i;// 00,01,10,11
    end
  
   #5 $finish;
end
  
initial 
begin
 // dumps all values whenever there is a change in any.
$monitor( IN0, IN1, IN2, IN3, S1, S0,OUTPUT);
// Uncomment the next two lines if you want to see the timing diagram as well
$dumpfile("dump.vcd");// vcd=value change dump
$dumpvars(1); // dump all variables in the wave form
end
​
​
endmodule

design.sv

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module MUX2(f,s,w0,w1);
input s,w0,w1;
output f;
​
 // Using gate level assignement
  wire sn, andout0, andout1;
  not (sn,s);
  and (andout0, sn,w0);
  and (andout1, s ,w1);
  or(f,andout0,andout1);
​
  
endmodule
​
module MUX4(f,s0,s1,w0,w1,w2,w3);
​
  input s0,s1,w0,w1,w2,w3;
  output f;
  
  wire tmp0,tmp1;
​
  MUX2 M0 (tmp0, s0,w0,w1);
  MUX2 M1 (tmp1, s0,w2,w3);
  MUX2 M2 (f, s1,tmp0,tmp1);
  
endmodule
​

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