verilog_functions - EDA Playground
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module function_example();
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  // Declare a simple static function
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  function integer easy_example (input integer a);
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    easy_example = a;
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  endfunction
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  // Basic addition example function
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  function integer addition (input integer in_a, in_b);
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    // Return the sum of the two inputs
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    addition = in_a + in_b;
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  endfunction
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  // Declaration of an automatic function  
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  function automatic integer factorial (input integer a);
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    begin
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      if (a > 1) begin
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        factorial = a * factorial(a - 1);
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      end
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      else begin
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        factorial = 1;
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      end
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    end
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  endfunction  
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  // Variable to store function returns
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  integer rtn;
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  initial begin
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    // Call basic function example
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    rtn = easy_example(10);
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    $display("Basic function example returned %0d", rtn);
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    // Call the basic addition example
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    rtn = addition(1, 1);
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    $display("addition function return %0d", rtn);
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    // Call the automatic function
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    rtn = factorial(5);
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    $display("factorial of 5 = %0d", rtn);
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  end
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endmodule
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// Code your design here
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In this example we show how to declare and call [verilog functions](https://www.fpgatutorial.com/verilog-function-and-task/#verilog-function).

In this example we show how to declare and call verilog functions.

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