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testbench.sv

 
/*
module tb;
  wire clk1;
  wire clk2;
  
  clock_gen u0(clk1);
  clock_gen #(.PHASE(270)) u1(clk2);
  
  initial begin
    #200 u1._disable();
    #95 u1._enable();
    #300 $finish;
  end
  
  initial begin
    $dumpvars;
    $dumpfile("dump.vcd");
  end
endmodule
*/
​
module tb;
  wire clk1;
  wire clk2;
  wire clk3;
  wire clk4;
  reg  enable;
  reg [7:0] dly;
  
  clock_gen u0(enable, clk1);
  clock_gen #(.PHASE(90)) u1(enable, clk2);
  clock_gen #(.PHASE(180)) u2(enable, clk3);
  clock_gen #(.PHASE(270)) u3(enable, clk4);
  
  initial begin
    enable <= 0;
    
    for (int i = 0; i < 10; i= i+1) begin
      dly = $random;
      #(dly) enable <= ~enable;      
      $display("i=%0d dly=%0d", i, dly);
      #50;
    end
    
    #50 $finish;
  end
  
  initial begin
    $dumpvars;
    $dumpfile("dump.vcd");
  end
endmodule
​

design.sv

xxxxxxxxxx
 
`timescale 1ns/1ps
​
/*
module clock_gen (output reg clk);
  
  parameter FREQ = 100000;  // in kHZ
  parameter PHASE = 0;      // in degrees
  parameter DUTY = 50;      // in percentage 
  
  real clk_pd       = 1.0/(FREQ * 1e3) * 1e9;   // convert to ns
  real clk_on       = DUTY/100.0 * clk_pd;
  real clk_off      = (100.0 - DUTY)/100.0 * clk_pd;
  real quarter      = clk_pd/4;
  real start_dly     = quarter * PHASE/90;
  
  reg enable;
  
  initial begin
    
    $display("FREQ    = %0d kHz", FREQ);
    $display("PHASE   = %0d deg", PHASE);
    $display("DUTY    = %0d %%",  DUTY);
    
    $display("PERIOD  = %0.3f ns", clk_pd);    
    $display("CLK_ON  = %0.3f ns", clk_on);
    $display("CLK_OFF = %0.3f ns", clk_off);
    $display("QUARTER = %0.3f ns", quarter);
    $display("START_DLY = %0.3f ns", start_dly);
  end
  
  initial begin
    clk     <= 0;
    enable  <= 0;
    
    // Initial delay to setup phasing
    #(start_dly) clk <= 1;
    
    // Enable clock
    enable <= 1;
  end
  
  always begin
    // When clock is enabled, maintain clk on/off periods
    if (enable) begin
        #(clk_on)  clk <= 0;
        #(clk_off) clk <= 1;
      
    // When clock is off, then set clk to zero and wait
    // for clock to be enabled
    end else begin
        clk <= 0;
        @(posedge enable);
    end
  end
  
  function _enable();
    enable = 1;
  endfunction
    
    function _disable();
      enable = 0;
    endfunction
 
endmodule
*/
​
module clock_gen (  input      enable,
                    output reg clk);
  
  parameter FREQ = 100000;  // in kHZ
  parameter PHASE = 0;      // in degrees
  parameter DUTY = 50;      // in percentage 
  
  real clk_pd       = 1.0/(FREQ * 1e3) * 1e9;   // convert to ns
  real clk_on       = DUTY/100.0 * clk_pd;
  real clk_off      = (100.0 - DUTY)/100.0 * clk_pd;
  real quarter      = clk_pd/4;
  real start_dly     = quarter * PHASE/90;
  
  reg start_clk;
  
  initial begin    
    $display("FREQ      = %0d kHz", FREQ);
    $display("PHASE     = %0d deg", PHASE);
    $display("DUTY      = %0d %%",  DUTY);
    
    $display("PERIOD    = %0.3f ns", clk_pd);    
    $display("CLK_ON    = %0.3f ns", clk_on);
    $display("CLK_OFF   = %0.3f ns", clk_off);
    $display("QUARTER   = %0.3f ns", quarter);
    $display("START_DLY = %0.3f ns", start_dly);
  end
  
  initial begin
    clk <= 0;
    start_clk <= 0;
  end
  
  always @ (posedge enable or negedge enable) begin
    if (enable) begin
      #(start_dly) start_clk = 1;
    end else begin
      #(start_dly) start_clk = 0;
    end      
  end
  
  always @(posedge start_clk) begin
    if (start_clk) begin
        clk = 1;
      
        while (start_clk) begin
            #(clk_on)  clk = 0;
            #(clk_off) clk = 1;
        end
      
        clk = 0;
    end
  end 
endmodule
​

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