4 to 16 decoder with Immediate Assertion - EDA Playground
Warning! This exercise has been opened in another tab; autosave has been disabled. Close this tab or refresh to reactivate.

 Languages & Libraries

 Tools & Simulators

 Examples

204


27
 
1
package ABC;
2
class decoder;
3
  randc logic  [3:0] binary_in;
4
  rand bit enable;
5
  constraint c1 {binary_in < 15;};
6
endclass
7
endpackage
8
​
9
module tb_decoder();
10
11
   import ABC::decoder;
12
  decoder d2=new();
13
    reg [3:0] in,en;
14
  wire [15:0] decoder_out;
15
16
  decoder_using_case d1(in,decoder_out,en);
17
  initial begin
18
    for(int i=0;i<16;i++)
19
      begin
20
        d2.randomize();
21
        in = d2.binary_in;
22
        en = d2.enable;
23
               #10;
24
        $display("enable = %d, decoder input = %h and output = %h", en,d2.binary_in, decoder_out);
25
      end
26
  end
27
endmodule
xxxxxxxxxx
1
36
 
1
// Code your design here
2
// Code your design here
3
module decoder_using_case (
4
input  bit [3:0]  binary_in   , //  4 bit binary input
5
output reg  [15:0] decoder_out , //  16-bit out
6
input  bit        enable        //  Enable for the decoder
7
);
8
​
9
always_comb
10
begin
11
  decoder_out = 0;
12
  if (enable==1) begin
13
    case (binary_in)
14
      4'h0 : decoder_out = 16'h0001;
15
      4'h1 : decoder_out = 16'h0002;
16
      4'h2 : decoder_out = 16'h0004;
17
      4'h3 : decoder_out = 16'h0009;
18
      4'h4 : decoder_out = 16'h0010;
19
      4'h5 : decoder_out = 16'h0020;
20
      4'h6 : decoder_out = 16'h0040;
21
      4'h7 : decoder_out = 16'h0080;
22
      4'h8 : decoder_out = 16'h0100;
23
      4'h9 : decoder_out = 16'h0200;
24
      4'hA : decoder_out = 16'h0400;
25
      4'hB : decoder_out = 16'h0800;
26
      4'hC : decoder_out = 16'h1000;
27
      4'hD : decoder_out = 16'h2000;
28
      4'hE : decoder_out = 16'h4000;
29
      4'hF : decoder_out = 16'h8000;
30
    endcase
31
    a1: assert (^decoder_out==1);
32
  end
33
34
end
35
endmodule
36
​
355 views and 0 likes     
 
when enable = 1, only one of the output signal line should be active, which can be asserted using bitwise xor operation in if loop.
I introduced a functional error when binary_in=3, expected output is 8 but i wrote 9, so that it should be asserted and pointed by simulator in log.

when enable = 1, only one of the output signal line should be active, which can be asserted using bitwise xor operation in if loop.
I introduced a functional error when binary_in=3, expected output is 8 but i wrote 9, so that it should be asserted and pointed by simulator in log.

2520:0