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EDA Playground lets you type in and run HDL code (using a selection of free and commercial simulators and synthesizers).
It's great for learning HDLs, it's great for testing out unfamiliar things and it's great for sharing code.

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testbench.sv

 
// Code your testbench here
// or browse Examples
`default_nettype none
​
module tb_counter;
  reg clk;                 
  reg rstn;                    
  wire [3:0] out;             
​
  counter uut(clk,rstn,out);
​
  // Generate a clock that should be driven to design
  // This clock will flip its value every 5ns -> time period = 10ns -> freq = 100 MHz
  always #5 clk = ~clk;
​
  // This initial block forms the stimulus of the testbench
  initial 
    begin
    
      clk <= 0;
      rstn <= 0;
    #20   
      rstn <= 1;                   
    #80  
      rstn <= 0;
    #50   
      rstn <= 1;
    
    #200 
      $finish;
  end
  
  initial begin
    $dumpvars(0,uut);
    $dumpfile("dump.vcd");
  end
endmodule

design.sv

xxxxxxxxxx
 
// Code your design here
`default_nettype none
module counter (  input clk,              
                  input rstn,              
                  output reg[3:0] out);    // Declare 4-bit output port to get the counter values
​
  // This always block will be triggered at the rising edge of clk (0->1)
  // Once inside this block, it checks if the reset is 0, if yes then change out to zero
  // If reset is 1, then design should be allowed to count up, so increment counter
  always @ (posedge clk) begin
    if (rstn <= 0)
      out <= 0;
    else 
      out <= out + 1;
  end
endmodule
​
//look up how to generate clock in FPGA
​
//https://www.edaplayground.com/x/rux

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