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using EDA Playground
VHDL
Verilog/SystemVerilog
UVM
EasierUVM
SVAUnit
SVUnit
VUnit (Verilog/SV)
VUnit (VHDL)
TL-Verilog
e + Verilog
Python + Verilog
Python Only
C++/SystemC

203

 
//----------------------------------------------------------------------//
//              example2 : Enumeration Type [DataTypes]                 //
//  This example shows how to declare enum, how to use the enumeration  //
//                  methods first and name                      // 
//----------------------------------------------------------------------//
​
module enum_datatype;
​
  //declaration
  enum { red, green, blue, yellow, white, black } Colors;
  
  //display members of Colors
  initial begin
    Colors = Colors.first;
    for(int i=0;i<6;i++) begin
      $display("Colors :: Value of  %0s \t is = %0d",Colors.name,Colors);
      Colors = Colors.next;      
    end
  end
  
endmodule

design.sv

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