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testbench.sv

 
//-------------------------------------------------------------------------
//                      www.verificationguide.com - Program Block
//-------------------------------------------------------------------------
//testbench
//-------------------------------------------------------------------------
program testbench(input bit [7:0] addr);
  initial begin
    $display("\t Addr = %0d",addr);
  end
endprogram
​
//-------------------------------------------------------------------------
//testbench top,
//-------------------------------------------------------------------------
module tbench_top;
  wire [7:0] addr;
  
  //design instance
  design_ex dut(addr);
  
  //testbench instance
  testbench test(addr);
​
endmodule

design.sv

 
//-------------------------------------------------------------------------
//design code
//-------------------------------------------------------------------------
module design_ex(output bit [7:0] addr);
  
  initial begin
    addr <= 10; 
  end     
endmodule

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