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//import uvm_pkg::*;
//`include "uvm_macros.svh"
//`include "seq_test.sv"
`include "seq_pkg.sv"
import seq_pkg::*;
`include "seq_if.sv"
module seq_test;
//bit clk;
//bit reset;
bit in;
bit out;
seq_if vif();
seq DUT(.in(vif.in),.out(vif.out));
/*initial
begin
forever #5 clk = ~clk;
end
initial begin
reset=1;
#5 reset=0;
end
*/
initial
begin
uvm_config_db#(virtual seq_if):: set(null,"*","seq_if",vif);
run_test("seq_top");
end
endmodule
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//`include "seq_item.sv"
//`include "seq_sequence.sv"
//`include "seq_env.sv"
class seq_top extends uvm_test;
`uvm_component_utils(seq_top)
seq_env env;
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env= seq_env::type_id::create("env", this);
endfunction
function void start_of_simulation_phase(uvm_phase phase);
super.start_of_simulation_phase(phase);
endfunction
virtual task run_phase(uvm_phase phase);
seq_sequence seq;
phase.raise_objection(.obj(this));
seq= seq_sequence::type_id::create("seq");
seq.start(env.agent.seq);
phase.drop_objection(.obj(this));
endtask
virtual function void end_of_elaboration();
uvm_report_info(get_full_name(),"End of elaboration",UVM_LOW);
print();
endfunction
endclass
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//`include "seq_agent.sv"
class seq_env extends uvm_env;
`uvm_component_utils(seq_env)
seq_agent agent;
function new(string name= "seq_env", uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
agent= seq_agent::type_id::create(.name("agent"), .parent(this));
endfunction
function void start_of_simulation_phase(uvm_phase phase);
super.start_of_simulation_phase(phase);
endfunction
endclass
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//`include "seq_driver.sv"
//`include "seq_monitor.sv"
class seq_agent extends uvm_agent;
`uvm_component_utils(seq_agent)
seq_driver driver;
seq_sequencer sequencer;
seq_monitor monitor;
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
driver= seq_driver::type_id::create("driver", this);
sequencer= seq_sequencer::type_id::create("sequencer", this);
monitor= seq_monitor::type_id::create("monitor", this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
driver.seq_item_port.connect(sequencer.seq_item_export);
endfunction
endclass
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`ifndef SEQ_ITEM
`define SEQ_ITEM
class seq_item extends uvm_sequence_item;
rand bit in;
bit out;
`uvm_object_utils_begin(seq_item)
`uvm_field_int(in, UVM_ALL_ON)
`uvm_field_int(out, UVM_ALL_ON)
`uvm_object_utils_end
function new(string name="seq_item");
super.new(name);
endfunction
endclass
`endif
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`ifndef SEQ_SEQUENCER
`define SEQ_SEQUENCER
//`include "seq_sequence.sv"
class seq_sequencer extends uvm_sequencer#(seq_item);
`uvm_component_utils(seq_sequencer)
function new(string name= "seq_sequencer", uvm_component parent);
super.new(name,parent);
endfunction
endclass
`endif
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`ifndef SEQ_DRIVER
`define SEQ_DRIVER
//`include "seq_sequencer.sv"
class seq_driver extends uvm_driver #(seq_item);
`uvm_component_utils(seq_driver)
seq_item seq;
virtual seq_if vif;
function new(string name="seq_sequencer", uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
if(!uvm_config_db#(virtual seq_if)::get(this,"","seq_if",vif))
`uvm_fatal("NO_VIF",{"virtual interface must be set for:",get_full_name(),".vif"});
endfunction
virtual task run_phase(uvm_phase phase);
forever
begin
seq_item_port.get_next_item(seq);
`uvm_info(get_full_name(),$psprintf("in=%0b,out=%0b",vif.in,vif.out),UVM_NONE)
drive();
seq_item_port.item_done();
end
endtask
virtual task drive();
vif.in= seq.out;
seq.out=vif.out;
endtask
endclass
`endif
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class seq_monitor extends uvm_monitor;
`uvm_component_utils(seq_monitor)
virtual seq_if vif;
uvm_analysis_port #(seq_item)item_collected_port;
seq_item seq_h;
function new(string name="seq_monitor", uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
seq_h= seq_item::type_id::create("seq",this);
if(!uvm_config_db#(virtual seq_if)::get(this,"","seq_if",vif))
`uvm_fatal("NOVIF",{"virtual interface must be set for:", get_full_name(), ".vif"});
endfunction
virtual task run_phase(uvm_phase phase);
begin
seq_h.in=vif.in;
vif.out=seq_h.out;
end
repeat(20)begin
`uvm_info(get_full_name(),$psprintf("in=%0b,out=%0b",seq_h.in,vif.out),UVM_NONE)
end
endtask
endclass
`ifndef SEQ_SEQUENCE
`define SEQ_SEQUENCE
//`include "seq_item.sv"
class seq_sequence extends uvm_sequence#(seq_item);
`uvm_object_utils(seq_sequence)
function new(string name="seq_sequence");
super.new(name);
endfunction
seq_item seq_h;
virtual task body;
repeat(20)begin
seq_h=seq_item::type_id::create("seq_h");
`uvm_do(seq_h);
end
endtask
endclass
`endif
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//`include "seq_item.sv"
//`include "seq_sequence.sv"
//`include "seq_env.sv"
class seq_top extends uvm_test;
`uvm_component_utils(seq_top)
seq_env env;
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env= seq_env::type_id::create("env", this);
endfunction
function void start_of_simulation_phase(uvm_phase phase);
super.start_of_simulation_phase(phase);
endfunction
virtual task run_phase(uvm_phase phase);
seq_sequence seq;
phase.raise_objection(.obj(this));
seq= seq_sequence::type_id::create("seq");
seq.start(env.agent.sequencer);
phase.drop_objection(.obj(this));
endtask
virtual function void end_of_elaboration();
uvm_report_info(get_full_name(),"End of elaboration",UVM_LOW);
print();
endfunction
endclass
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package seq_pkg;
import uvm_pkg::*;
`include "seq_item.sv"
`include "seq_sequence.sv"
`include "seq_sequencer.sv"
`include "seq_driver.sv"
`include "seq_monitor.sv"
`include "seq_agent.sv"
`include "seq_env.sv"
`include "seq_test.sv"
endpackage : seq_pkg
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module seq(out,in,reset,clk);
output out;
input in, reset,clk;
reg out;
reg [1:0] state;
parameter s0=2'b00,
s1=2'b01,
s2=2'b10,
s3=2'b11;
always @(posedge clk or reset)
if(reset)
begin
state <= s0;
out <= 0;
end
else
begin
case(state)
s0:if (in==1)
begin
out <= 0;
state <= s1;
end
else
begin
state <= s0;
out <= 0;
end
s1:if (in==0)
begin
out <= 0;
state <= s2;
end
else
begin
state <= s1;
out <= 0;
end
s2:if (in==1)
begin
out <= 0;
state <= s3;
end
else
begin
state <= s2;
out <= 0;
end
s3:if (in==1)
begin
out <= 1;
state <= s1;
end
else
begin
state <= s3;
out<= 0;
end
default:
begin
state <= s0;
out<=0;
end
endcase
end
endmodule
interface seq_if;
logic in;
logic out;
endinterface
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