Brno_Univ_of_Technology_Full adder example - EDA Playground
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1
----------------------------------------------------------
2
--
3
-- Testbench for full adder.
4
-- Nexys A7-50T, xc7a50ticsg324-1L
5
-- TerosHDL, Vivado v2020.2, EDA Playground
6
--
7
-- Copyright (c) 2019 Tomas Fryza
8
-- Dept. of Radio Electronics, Brno Univ. of Technology, Czechia
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-- This work is licensed under the terms of the MIT license.
10
--
11
----------------------------------------------------------
12
​
13
library ieee;
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  use ieee.std_logic_1164.all;
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​
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----------------------------------------------------------
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-- Entity declaration for testbench
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----------------------------------------------------------
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​
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entity tb_full_adder is
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-- Entity of testbench is always empty
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end entity tb_full_adder;
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​
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----------------------------------------------------------
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-- Architecture body for testbench
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----------------------------------------------------------
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​
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architecture testbench of tb_full_adder is
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​
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  -- Local signals for full adder
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  signal sig_a        : std_logic;
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  signal sig_b        : std_logic;
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  signal sig_carry_in : std_logic;
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  signal sig_sum      : std_logic;
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  signal sig_carry    : std_logic;
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​
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begin
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​
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  -- Connecting testbench signals with full_adder
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  -- entity (Unit Under Test)
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  uut_full : entity work.full_adder
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    port map (
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      a        => sig_a,
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      b        => sig_b,
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      carry_in => sig_carry_in,
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      sum      => sig_sum,
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      carry    => sig_carry
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    );
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​
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  --------------------------------------------------------
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  -- Data generation process
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  --------------------------------------------------------
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  p_stimulus : process is
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  begin
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​
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    report "Stimulus process started";
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​
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    sig_carry_in <= '0';
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    sig_b        <= '0';
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    sig_a        <= '0';
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    wait for 100 ns;
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    assert (
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        (sig_carry = '0') and
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        (sig_sum   = '0')
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      )  -- Expected output
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      report "Test failed for input combination 000"
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      severity error;
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​
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    sig_carry_in <= '0';
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    sig_b        <= '0';
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    sig_a        <= '1';
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    wait for 100 ns;
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    assert (
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        (sig_carry = '0') and
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        (sig_sum   = '1')
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      )
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      report "Test failed for input combination 001"
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      severity error;
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​
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    sig_carry_in <= '0';
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    sig_b        <= '1';
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    sig_a        <= '0';
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    wait for 100 ns;
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    assert (
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        (sig_carry = '0') and
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        (sig_sum   = '1')
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      )
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      report "Test failed for input combination 010"
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      severity error;
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​
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    sig_carry_in <= '0';
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    sig_b        <= '1';
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    sig_a        <= '1';
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    wait for 100 ns;
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    assert (
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        (sig_carry = '1') and
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        (sig_sum   = '0')
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      )
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      report "Test failed for input combination 011"
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      severity error;
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​
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    sig_carry_in <= '1';
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    sig_b        <= '0';
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    sig_a        <= '0';
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    wait for 100 ns;
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    assert (
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        (sig_carry = '0') and
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        (sig_sum   = '1')
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      )
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      report "Test failed for input combination 100"
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      severity error;
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​
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    sig_carry_in <= '1';
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    sig_b        <= '0';
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    sig_a        <= '1';
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    wait for 100 ns;
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    assert (
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        (sig_carry = '1') and
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        (sig_sum   = '0')
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      )
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      report "Test failed for input combination 101"
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      severity error;
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​
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    sig_carry_in <= '1';
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    sig_b        <= '1';
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    sig_a        <= '0';
127
    wait for 100 ns;
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    assert (
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        (sig_carry = '1') and
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        (sig_sum   = '0'))
131
      report "Test failed for input combination 110"
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      severity error;
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​
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    sig_carry_in <= '1';
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    sig_b        <= '1';
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    sig_a        <= '1';
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    wait for 100 ns;
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    assert (
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        (sig_carry = '1') and
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        (sig_sum   = '1')
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      )
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      report "Test failed for input combination 111"
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      severity error;
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​
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    report "Stimulus process finished";
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    wait;
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​
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  end process p_stimulus;
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​
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end architecture testbench;
151
​
xxxxxxxxxx
1
69
 
1
----------------------------------------------------------
2
--
3
--! @title Full adder
4
--! @author Tomas Fryza
5
--! Dept. of Radio Electronics, Brno Univ. of Technology, Czechia
6
--!
7
--! @copyright (c) 2019 Tomas Fryza
8
--! This work is licensed under the terms of the MIT license
9
--!
10
--! Implementation of full adder.
11
--
12
-- Hardware: Nexys A7-50T, xc7a50ticsg324-1L
13
-- Software: TerosHDL, Vivado 2020.2, EDA Playground
14
​
15
library ieee;
16
  use ieee.std_logic_1164.all;
17
​
18
----------------------------------------------------------
19
-- Entity declaration for full adder
20
----------------------------------------------------------
21
​
22
entity full_adder is
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  port (
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    a        : in    std_logic;
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    b        : in    std_logic;
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    carry_in : in    std_logic;
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    sum      : out   std_logic;
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    carry    : out   std_logic
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  );
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end entity full_adder;
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​
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----------------------------------------------------------
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-- Architecture body for full adder
34
----------------------------------------------------------
35
​
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architecture behavioral of full_adder is
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​
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  -- Internal signals between half adders
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  signal sig_sum0_a1 : std_logic;  -- From sum0 to a1
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  signal sig_carry0  : std_logic;
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  signal sig_carry1  : std_logic;
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​
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begin
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​
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  --------------------------------------------------------
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  -- Instance (copy) of the first half adder
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  half_adder0 : entity work.half_adder
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    port map (
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      a     => a,
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      b     => b,
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      sum   => sig_sum0_a1,
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      carry => sig_carry0
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    );
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​
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  --------------------------------------------------------
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  -- Instance (copy) of the second half adder
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  half_adder1 : entity work.half_adder
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    port map (
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      a     => sig_sum0_a1,
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      b     => carry_in,
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      sum   => sum,
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      carry => sig_carry1
63
    );
64
​
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  -- Output carry
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  carry <= sig_carry0 or sig_carry1;
67
​
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end architecture behavioral;
69
​
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Example of dataflow style modeling for half adder and structural style of modeling for full adder. Testbenches for both, half and full added entities.
​
For half adder simulation, parameter **Top entity** will be **tb_half_adder**.
For full adder simulation, parameter **Top entity** will be **tb_full_adder**.

Example of dataflow style modeling for half adder and structural style of modeling for full adder. Testbenches for both, half and full added entities.

For half adder simulation, parameter Top entity will be tb_half_adder.
For full adder simulation, parameter Top entity will be tb_full_adder.

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