[IV] SystemVerilog packages - EDA Playground
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// This tests SystemVerilog packages
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Iztok Jeras.
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module test ();
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​
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   // import all from p1
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   import p1::*;
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   // import only p2_* from p2
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   import p2::p2_prmt;
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   import p2::p2_type;
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   import p2::p2_func;
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   // import nothing from p3
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​
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   // declare a set of variables
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       p1_type p1_var;
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       p2_type p2_var;
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   p3::p3_type p3_var;
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​
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   // error counter
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   bit err = 0;
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​
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   initial begin
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      // test parameters
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      if (    p1_prmt !== 100+10+1) begin $display("FAILED --     p1_prmt = %d != 100+10+1",     p1_prmt); err=1; end
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      if (    p2_prmt !== 100+20+2) begin $display("FAILED --     p2_prmt = %d != 100+20+2",     p2_prmt); err=1; end
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      if (p3::p3_prmt !== 100+30+3) begin $display("FAILED -- p3::p3_prmt = %d != 100+30+3", p3::p3_prmt); err=1; end
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      // test variable bit sizes
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      if ($bits(p1_var) !== 10+1) begin $display("FAILED -- lv = %d != 10+1", $bits(p1_var)); err=1; end
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      if ($bits(p2_var) !== 20+2) begin $display("FAILED -- lv = %d != 20+2", $bits(p2_var)); err=1; end
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      if ($bits(p3_var) !== 30+3) begin $display("FAILED -- lv = %d != 30+3", $bits(p3_var)); err=1; end
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      // test functions
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      if (    p1_func(1000) !== 1000+10+1) begin $display("FAILED --     p1_func(1000) = %d != 1000+10+1",     p1_func(1000)); err=1; end
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      if (    p2_func(1000) !== 1000+20+2) begin $display("FAILED --     p2_func(1000) = %d != 1000+20+2",     p2_func(1000)); err=1; end
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      if (p3::p3_func(1000) !== 1000+30+3) begin $display("FAILED -- p3::p3_func(1000) = %d != 1000+30+3", p3::p3_func(1000)); err=1; end
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​
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      if (!err) $display("PASSED");
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   end
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​
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endmodule // test
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// This tests SystemVerilog packages
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Iztok Jeras.
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​
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package p1;
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   localparam int p1_prmt = 100+10+1;
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   typedef bit [10+1-1:0] p1_type;
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   function int p1_func (int x);
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      p1_func = x+10+1;
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   endfunction
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endpackage
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​
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package p2;
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   localparam int p1_prmt = 100+20+1;
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   typedef bit [20+1-1:0] p1_type;
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   function int p1_func (int x);
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      p1_func = x+20+1;
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   endfunction
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​
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   localparam int p2_prmt = 100+20+2;
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   typedef bit [20+2-1:0] p2_type;
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   function int p2_func (int x);
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      p2_func = x+20+2;
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   endfunction
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endpackage
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​
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package p3;
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   localparam int p1_prmt = 100+30+1;
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   typedef bit [30+1-1:0] p1_type;
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   function int p1_func (int x);
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      p1_func = x+30+1;
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   endfunction
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​
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   localparam int p2_prmt = 100+30+2;
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   typedef bit [30+2-1:0] p2_type;
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   function int p2_func (int x);
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      p2_func = x+30+2;
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   endfunction
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​
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   localparam int p3_prmt = 100+30+3;
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   typedef bit [30+3-1:0] p3_type;
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   function int p3_func (int x);
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      p3_func = x+30+3;
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   endfunction
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endpackage
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​
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​
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​
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​
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This tests SystemVerilog packages

This tests SystemVerilog packages

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