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// Code your testbench here
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// or browse Examples
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​
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`include "riscv_pkg.sv"
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`include "riscv_fetch.sv"
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`include "riscv_decode.sv"
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`include "riscv_regfile.sv"
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`include "riscv_execute.sv"
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`include "riscv_dmem.sv"
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`include "riscv_control.sv"
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​
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module riscv_top (
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  input       wire        clk,
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  input       wire        reset,
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  output      wire        imem_psel_o,
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  output      wire        imem_penable_o,
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  output      wire[31:0]  imem_paddr_o,
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  output      wire        imem_pwrite_o,
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  output      wire[31:0]  imem_pwdata_o,
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  input       wire        imem_pready_i,
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  input       wire[31:0]  imem_prdata_i,
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  output      wire        dmem_psel_o,
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  output      wire        dmem_penable_o,
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  output      wire[31:0]  dmem_paddr_o,
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  output      wire        dmem_pwrite_o,
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  output      wire[31:0]  dmem_pwdata_o,
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  input       wire        dmem_pready_i,
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  input       wire[31:0]  dmem_prdata_i
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);
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  wire          instr_done;
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  wire          if_dec_valid;
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  wire [31:0]   if_dec_instr;
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  wire [31:0]   ex_if_pc;
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  wire [4:0]    rs1;
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  wire [4:0]    rs2;
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  wire [4:0]    rd;
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  wire [6:0]    op;
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  wire [2:0]    funct3;
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  wire [6:0]    funct7;
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  logic         is_r_type;
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  logic         is_i_type;
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  logic         is_s_type;
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  logic         is_b_type;
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  logic         is_u_type;
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  logic         is_j_type;
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  logic[11:0]   i_type_imm;
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  logic[11:0]   s_type_imm;
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  logic[11:0]   b_type_imm;
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  logic[19:0]   u_type_imm;
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  logic[19:0]   j_type_imm;
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  logic[1:0]    pc_sel;
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  logic         op1_sel;
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  logic[1:0]    op2_sel;
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  logic[1:0]    wb_sel;
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  logic         pc4_sel;
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  logic         mem_wr;
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  logic         cpr_en;
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  logic         rf_en;
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  logic[3:0]    alu_op;
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  wire          rf_wr_en;
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  wire[4:0]     rf_wr_addr;
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  wire[31:0]    rf_wr_data;
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  wire[4:0]     rf_rd_p0;
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  wire[4:0]     rf_rd_p1;
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  wire[31:0]    rf_rd_p0_data;
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  wire[31:0]    rf_rd_p1_data;
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  wire [31:0]   opr_a;
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  wire [31:0]   opr_b;
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  wire [3:0]    op_sel;
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  wire [31:0]   ex_res;
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  wire          ex_dmem_valid;
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  wire[31:0]    ex_dmem_addr;
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  wire[31:0]    ex_dmem_wdata;
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  wire          ex_dmem_wnr;
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  logic[31:0]   dmem_data;
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  logic         dmem_done;
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  logic[31:0]   imm_sign_ext;
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  logic         mem_op;
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  // Instantiate and connect all the submodules
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  assign instr_done = dmem_done | ~mem_op;
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  riscv_fetch FETCH (
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    .clk                (clk),
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    .reset              (reset),
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    .instr_done_i       (instr_done),
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    .psel_o             (imem_psel_o),
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    .penable_o          (imem_penable_o),
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    .paddr_o            (imem_paddr_o),
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    .pwrite_o           (imem_pwrite_o),
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    .pwdata_o           (imem_pwdata_o),
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    .pready_i           (imem_pready_i),
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    .prdata_i           (imem_prdata_i),
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    .if_dec_valid_o     (if_dec_valid),
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    .if_dec_instr_o     (if_dec_instr),
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    .ex_if_pc_i         (ex_if_pc)
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  );
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  riscv_decode DECODE (
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    .if_dec_instr_i     (if_dec_instr),
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    .rs1_o              (rs1),
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    .rs2_o              (rs2),
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    .rd_o               (rd),
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    .op_o               (op),
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    .funct3_o           (funct3),
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    .funct7_o           (funct7),
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    .is_r_type_o        (is_r_type),
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    .is_i_type_o        (is_i_type),
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    .is_s_type_o        (is_s_type),
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    .is_b_type_o        (is_b_type),
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    .is_u_type_o        (is_u_type),
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    .is_j_type_o        (is_j_type),
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    .i_type_imm_o       (i_type_imm),
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    .s_type_imm_o       (s_type_imm),
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    .b_type_imm_o       (b_type_imm),
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    .u_type_imm_o       (u_type_imm),
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    .j_type_imm_o       (j_type_imm)
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  );
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  assign rf_wr_en = rf_en;
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  assign rf_wr_addr = rd;
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  assign rf_wr_data = wb_sel[0] ? ex_res :
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    wb_sel[1] ? ex_if_pc + 32'h4 :
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    dmem_data;
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  riscv_regfile REGFILE (
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    .clk                (clk),
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    .reset              (reset),
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    .rf_wr_en_i         (rf_wr_en),
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    .rf_wr_addr_i       (rf_wr_addr),
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    .rf_wr_data_i       (rf_wr_data),
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    .rf_rd_p0_i         (rf_rd_p0),
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    .rf_rd_p1_i         (rf_rd_p1),
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    .rf_rd_p0_data_o    (rf_rd_p0_data),
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    .rf_rd_p1_data_o    (rf_rd_p1_data)
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  );
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  // Sign extend the immediate
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  assign imm_sign_ext = (is_i_type) ? {{30{i_type_imm[11]}}, i_type_imm} :
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                        (is_s_type) ? {{30{s_type_imm[11]}}, s_type_imm} :
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                        (is_b_type) ? {{30{b_type_imm[11]}}, b_type_imm} :
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                        (is_u_type) ? {{12{u_type_imm[19]}}, u_type_imm} :
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                                      {{12{j_type_imm[19]}}, j_type_imm};
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  // Send the correct data to the ALU
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  assign opr_a = op1_sel ? imm_sign_ext : rf_rd_p0_data;
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  assign opr_b = &op2_sel   ? rf_rd_p1_data :
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                 op2_sel[0] ? imm_sign_ext :
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                              ex_if_pc;
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  riscv_execute EXECUTE (
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    .opr_a_i            (opr_a),
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    .opr_b_i            (opr_b),
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    .op_sel_i           (alu_op),
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    .ex_res_o           (ex_res)
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  );
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  assign mem_op = is_s_type | (is_i_type & (op == 7'h3));
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  assign dmem_valid = if_dec_valid & mem_op;
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  assign ex_dmem_addr = ex_res;
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  assign ex_dmem_wnr = mem_wr;
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  assign ex_dmem_wdata = rf_rd_p0_data;
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  riscv_dmem DMEM (
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    .clk                (clk),
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    .reset              (reset),
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    .ex_dmem_valid_i    (ex_dmem_valid), // Mem operation is valid
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    .ex_dmem_addr_i     (ex_dmem_addr),
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    .ex_dmem_wdata_i    (ex_dmem_wdata),
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    .ex_dmem_wnr_i      (ex_dmem_wnr), // 1 - write, 0 - read
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    .psel_o             (dmem_psel_o),
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    .penable_o          (dmem_penable_o),
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    .paddr_o            (dmem_paddr_o),
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    .pwrite_o           (dmem_pwrite_o),
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    .pwdata_o           (dmem_pwdata_o),
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    .pready_i           (dmem_pready_i),
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    .prdata_i           (dmem_prdata_i),
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    .dmem_data_o        (dmem_data),
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    .dmem_done_o        (dmem_done)
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  );
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  riscv_control CONTROL (
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    .instr_funct3_i     (funct3),
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    .instr_funct7_i     (funct7),
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    .instr_op_i         (op),
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    .is_r_type_i        (is_r_type),
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    .is_i_type_i        (is_i_type),
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    .is_s_type_i        (is_s_type),
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    .is_b_type_i        (is_b_type),
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    .is_u_type_i        (is_u_type),
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    .is_j_type_i        (is_j_type),
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    .pc_sel_o           (pc_sel),
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    .op1_sel_o          (op1_sel),
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    .op2_sel_o          (op2_sel),
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    .wb_sel_o           (wb_sel),
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    .pc4_sel_o          (pc4_sel),
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    .mem_wr_o           (mem_wr),
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    .cpr_en_o           (/* TODO */),
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    .rf_en_o            (rf_en),
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    .alu_op_o           (alu_op)
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  );
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endmodule
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A single cycle RISC-V processor: RV32I Top - 3

A single cycle RISC-V processor: RV32I Top - 3

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