interface binding with wrapper

 
`include "uvm_macros.svh"
`include "interf_wrapper.sv"
​
// TOP MODULE    
module top;
    
  import uvm_pkg::*; 
  import interf_pkg::*;
  
  
  logic clk, reset;  
  
  initial begin
    clk = 0;
    reset = 1;
    repeat(3) @(posedge clk);
    reset = 0;
    #1000;
    foreach(interf_instances[i])
      `uvm_info("INTERF INSTANCES", $sformatf("%s", interf_instances[i]), UVM_LOW)
    $finish;
  end
  
  always begin
    clk = #10 ~clk;
  end
  
  dut #(100) dut_inst1(clk, reset);
  dut #(200) dut_inst2(clk, reset);
  dut #(300) dut_inst3(clk, reset);
  dut #(400) dut_inst4(clk, reset);
    
  bind dut interf_wrapper if_wrp( // Bind interf_wrapper to all dut instances
    .clk(i_clk),
    .reset(i_reset),
    .en(o_en),
    .data(o_data),
    .out(o_out)  
  );
  
  //Dump waves
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, top);
  end
  
endmodule
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//A package to import somewhere in the begining so it can be accessed by all components
package interf_pkg;
string interf_instances[$];
endpackage
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interface interf_wrapper(
  
  input logic clk, 
  input logic reset, 
  input logic en,
  input logic [7:0] data,
  input logic out);
  
  interf if_(
       .clk(clk),
       .en(en),
       .data(data),
       .out(out)
   );
​
  string interf_name;
 
  //Get name of interface and set it to config db
  initial begin
        interf_name = $sformatf("if_%s", if_.interf_name);
        `uvm_info($sformatf("interf_wrapper_%s", interf_name),$sformatf("setting %s to config db",interf_name),UVM_HIGH)
        uvm_config_db#(virtual interf)::set(null,"*",interf_name ,if_); 
  end
​
​
endinterface
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design.sv

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`include "interf_pkg.sv"
import interf_pkg::*;
​
interface interf(
  
  input logic clk, 
  input logic reset, 
  input logic en,
  input logic [7:0] data,
  input logic out);
  
  string interf_name =  $sformatf("%m");    
  
  //Every time that interf is instantiated, the name will be added to a queue
  initial begin
    interf_instances.push_back(interf_name);
  end
​
endinterface
​
///////////////////////////////////////////////////////////////////
module dut#(parameter MAX_RANGE = 100) (
  
  input logic i_clk, 
  input logic i_reset, 
  output logic o_en,
  output logic [7:0] o_data,
  output logic o_out);
  
  always @(posedge i_reset) begin
      o_out <= 0; 
      o_en <= 0;
      o_data <= 0;
  end
  
  always @(posedge i_clk) begin 
    if(!i_reset) begin
      o_out <= o_en; 
      o_en <= $urandom_range(0,1);
      o_data <= $urandom_range(0,MAX_RANGE);
    end
  end
  
endmodule

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