Pattern Detector 10110 in SV(no FSM)

testbench.sv

 
// Code your testbench here
// or browse Examples
module test;
  reg clk=0;
  reg rst=1;
  reg in=0;
  wire flag;
  
  pattern_detect pat(.clk(clk), .rst(rst), .in(in), .flag(flag));
  
  initial begin
    forever begin
    #10 clk = ~clk;
    end
  end
  initial begin
     // Dump waves
    $dumpfile("dump.vcd");
    $dumpvars(1, test);
    
    #10 rst=0;
   
    in=0;
    #20 in=1;
    #20 in=1;
    #20 in=0;
    #20 in=1;
    #20 in=1;
    #20 in=0;
    #20 in=1;
    #20 in=0;
    #20 in=0;
    #20 in=1;
    #20 in=0;
    #20 in=1;
     
    $finish;
    
    
  end
  
endmodule
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design.sv

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// Code your design here
module pattern_detect(input clk, input rst, input bit in, output flag);
  logic  pat_seq[$]='{1,0,1,1,0};
  logic  pat_in[$]='{0,0,0,0,0};
  reg  flag=0;
  
  always @(posedge clk) begin
    if(!rst) begin
      pat_in.pop_front();
      pat_in.push_back(in);
​
      if(pat_in == pat_seq) begin
        flag <= 1;  
        $display("***************************");
        $display("flag is 1 @time=%0d", $time);
        $display("***************************");
        foreach(pat_in[i]) begin
          $display("pat_in[%0d]=%0d", i, pat_in[i]);
        end
        $display("***************************");
      end
      else begin
        flag <= 0;
        $display("flag is 0 @time=%0d", $time);
        foreach(pat_in[i]) begin
          $display("pat_in[%0d]=%0d", i, pat_in[i]);
        end
        //$display("flag design=%0d, @time=%0d", flag, $time);
​
      end
    end
    if(rst) 
      flag <=0 ;
    
    //$display("flag=%0d @time=%0d", flag, $time)
    
  end
  
endmodule

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