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using EDA Playground
VHDL
Verilog/SystemVerilog
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C++/SystemC

208

 
module m;
​
  typedef struct {
    bit        enable_1;
    bit [31:0] addr_1; 
  } mem_pkt_1; 
  
​
typedef struct {
    bit        enable_2;
  bit [31:0] addr_2; 
} mem_pkt_2; 
  
  
  mem_pkt_1 pkt1,q1[$];
  mem_pkt_2 pkt2,q2[$];
  
initial   begin
  
  $display ("pkt1 = %p", pkt1);
  $display ("pkt2 = %p", pkt2);
  
  pkt1.addr_1 = 32'h25a0_0CDF;
  pkt1.enable_1 = 0;
  
  pkt2.addr_2 = 32'h25a0_0CDF;
  pkt2.enable_2 = 0;
  
    $display ("pkt1 = %p", pkt1);
  $display ("pkt2 = %p", pkt2);
  
  q1.push_back(pkt1);
 q2.push_back(pkt2);
  
  if ( q1.size == q2.size && 
     q1.and(i1) with (i1.addr_1 == q2[i1.index].addr_2 && i1.enable_1 == q2[i1.index].enable_2) )
  $display("q1 == q2");
else
  $display("q1 != q2");
  end
endmodule

design.sv

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