4-bit adder subtractor using 1 bit adder - EDA Playground
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module RCAS_TB;
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  wire [3:0] S, Cout;
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  reg [3:0] A, B;
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  reg ctrl;
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  ripple_carry_adder_subtractor rcas(A, B, ctrl, S, Cout);
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  initial begin
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    $monitor("CTRL=%b: A = %b, B = %b --> S = %b, Cout[3] = %b", ctrl, A, B, S, Cout[3]);
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    ctrl = 0;
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    A = 1; B = 0;
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    #3 A = 2; B = 4;
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    #3 A = 4'hb; B = 4'h6;
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    #3 A = 5; B = 3;
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    ctrl = 1;
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    A = 1; B = 0;
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    #3 A = 2; B = 4;
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    #3 A = 4'hb; B = 4'h6;
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    #3 A = 5; B = 3;
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    #3 $finish;
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  end
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  initial begin
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    $dumpfile("waves.vcd");
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    $dumpvars;
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  end
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endmodule
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module full_adder(
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  input a, b, cin,
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  output sum, cout
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);
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  assign {sum, cout} = {a^b^cin, ((a & b) | (b & cin) | (a & cin))};
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  //or
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  //assign sum = a^b^cin;
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  //assign cout = (a & b) | (b & cin) | (a & cin);
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endmodule
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​
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module ripple_carry_adder_subtractor #(parameter SIZE = 4) (
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  input [SIZE-1:0] A, B,
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  input CTRL,
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  output [SIZE-1:0] S, Cout);
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  bit [SIZE-1:0] Bc;
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  genvar g;
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  assign Bc[0] = B[0] ^ CTRL;
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  full_adder fa0(A[0], Bc[0], CTRL, S[0], Cout[0]);
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  generate  // This will instantial full_adder SIZE-1 times
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    for(g = 1; g<SIZE; g++) begin
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      assign Bc[g] = B[g] ^ CTRL;
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      full_adder fa(A[g], Bc[g], Cout[g-1], S[g], Cout[g]);
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    end
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  endgenerate
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endmodule
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