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using EDA Playground
VHDL
Verilog/SystemVerilog
UVM
EasierUVM
SVAUnit
SVUnit
VUnit (Verilog/SV)
VUnit (VHDL)
TL-Verilog
e + Verilog
Python + Verilog
Python Only
C++/SystemC

206

 
// Code your testbench here
// or browse Examples
​
typedef enum { L2_PKT, L3_PKT, JUMBO_PKT } pkt_type_t;
​
class gen_pkt;
  int cell_size = 128;
  int pkt_len;
  rand pkt_type_t pkt_type;
  int pattern;
  rand int num_pkts, pkt_len_mode;
  pkt_type_t list_of_pkts[];
    
  constraint c1 { pattern dist {
    1 := 20, 2 := 50, 3 := 30 }; 
                };
  
  constraint c2 { 
    pkt_len_mode dist {
      1 := 10, 2 := 10, 3 := 10, 4 := 20, 5 := 10, 6 := 10, 7 := 30 };
    pkt_len_mode == 1 -> pkt_len == 64;
    pkt_len_mode == 2 -> pkt_len == (pkt_type == L2_PKT) ? 1518 : (pkt_type == L3_PKT) ? 4096 : 9216;
    pkt_len_mode == 3 -> pkt_len == pkt_len%cell_size;
    pkt_len_mode == 4 -> pkt_len inside {[pkt_len%cell_size-4:pkt_len%cell_size+4]};
    //pkt_len_mode == 5 -> pkt_len += 1;
    //pkt_len_mode == 6 -> pkt_len -= 1;
    pkt_len_mode == 7 -> pkt_len inside {[64:9216]};
  };
endclass
​
module top;
  reg clk;
  
  gen_pkt A;
  
  initial begin
    clk <= 0;
    A = new();
    $display("[%t]", $time);
  end
  
  always begin
    #10 clk <= clk;
  end
  
  //task gen_pkt() begin
  //end
endmodule 

design.sv

 
// Code your design here
​

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