Simple cocotb Adder tests - EDA Playground
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# CVC www.cvcblr.com Trying COCOTB & Pyhton
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# This is NEWBIE code in Python, so don't expect too much
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# Simple test for an AND Gate module
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#
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# Use the ccotb framework
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import cocotb
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# Use Timer to model Verilog like #delays
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from cocotb.triggers import Timer
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# Use Reporting mechanism, a la UVM messaging
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from cocotb.result import TestFailure
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# Start a testcase
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@cocotb.test()
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def dir_test (dut): # dut is the defult, pre-defined pointer to DUT top Verilog module, done already by Cocotb for us
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    """Test for few patterns"""
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    dut.log.info("Start of test!")
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    # Wait for 10 ns, Cocotb's Timer argument is in PS i.e. timer_ps
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    yield Timer(10000)
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    dut.log.info("Drive 1 & 0 to AND Gate!")
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    dut.a = 1
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    dut.b = 0
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    # Wait for 10 ns
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    yield Timer(10000)
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    if dut.c != 0:
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        raise TestFailure(
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            "AND Gate failed - not really possible..still.. result is incorrect: %s != 0" % str(dut.c)) 
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    else: # these last two lines are not strictly necessary
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        dut.log.info("PASS!")
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    # Let's create a 1 && 1 case
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    dut.log.info("Drive 1 & 1 to AND Gate!")
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    dut.a = 1
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    dut.b = 1
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    # Wait for 10 ns
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    yield Timer(10000)
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    # Use wrong EXPECT - to see some failure in Cocotb for fun!
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    if dut.c != 0:
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        raise TestFailure(
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            "AND Gate failed - not really possible..still.. result is incorrect: %s != 0" % str(dut.c)) 
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    else: # these last two lines are not strictly necessary
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        dut.log.info("PASS!")
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`timescale 1ns/1ns
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// Simple AND gate DUT
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module and_gate (input a, b,
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                 output reg c);
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  always @(*) begin
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    c = a && b;
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  end
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endmodule
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Very simple cocotb example

Very simple cocotb example

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