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* Icarus Verilog 0.9.7 not available.
202
# CVC www.cvcblr.com Trying COCOTB & Pyhton
# This is NEWBIE code in Python, so don't expect too much
# Simple test for an AND Gate module
#
# Use the ccotb framework
import cocotb
# Use Timer to model Verilog like #delays
from cocotb.triggers import Timer
# Use Reporting mechanism, a la UVM messaging
from cocotb.result import TestFailure
# Start a testcase
@cocotb.test()
def dir_test (dut): # dut is the defult, pre-defined pointer to DUT top Verilog module, done already by Cocotb for us
"""Test for few patterns"""
dut.log.info("Start of test!")
# Wait for 10 ns, Cocotb's Timer argument is in PS i.e. timer_ps
yield Timer(10000)
dut.log.info("Drive 1 & 0 to AND Gate!")
dut.a = 1
dut.b = 0
# Wait for 10 ns
yield Timer(10000)
if dut.c != 0:
raise TestFailure(
"AND Gate failed - not really possible..still.. result is incorrect: %s != 0" % str(dut.c))
else: # these last two lines are not strictly necessary
dut.log.info("PASS!")
# Let's create a 1 && 1 case
dut.log.info("Drive 1 & 1 to AND Gate!")
dut.a = 1
dut.b = 1
# Wait for 10 ns
yield Timer(10000)
# Use wrong EXPECT - to see some failure in Cocotb for fun!
if dut.c != 0:
raise TestFailure(
"AND Gate failed - not really possible..still.. result is incorrect: %s != 0" % str(dut.c))
else: # these last two lines are not strictly necessary
dut.log.info("PASS!")
xxxxxxxxxx
`timescale 1ns/1ns
// Simple AND gate DUT
module and_gate (input a, b,
output reg c);
always @(*) begin
c = a && b;
end
endmodule
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