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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Simulacion is
--
end Simulacion;
architecture Behavioral of Simulacion is
component Alto_nivel
Port ( clk : in STD_LOGIC;
inicio : in STD_LOGIC;
reinicio : in STD_LOGIC;
infrarrojo : in STD_LOGIC;
Data_out : out STD_LOGIC_VECTOR (5 downto 0)
);
end component;
-- Señales de las entradas
signal clk, inicio, reinicio, infrarrojo : STD_LOGIC:= '0';
-- Señales de salidas
signal Data_out : STD_LOGIC_VECTOR (5 downto 0):= (others => '0');
constant PERIOD : time := 10 ns;
begin
process begin
clk <= '0';
wait for PERIOD/2;
clk <= '1';
wait for PERIOD/2;
end process;
UO: Alto_nivel port map (
clk => clk,
inicio => inicio,
reinicio => reinicio,
infrarrojo => infrarrojo,
Data_out => Data_out
);
process begin
--- Estímulos de la simulación wait for 100 ns;
wait for 50 ns;
--- Escribiendo en la memoria
reinicio <= '1';
wait for 50 ns;
reinicio <= '0';
wait for 150 ns;
-- Empieza la carrera
inicio <= '1';
wait for 20 ns;
inicio <= '0';
wait for 520 ns;
infrarrojo <= '1'; -- Llega el 1 corredor
wait for 15 ns;
infrarrojo <= '0';
wait for 60 ns;
infrarrojo <= '1'; -- Llega el 2 corredor
wait for 15 ns;
infrarrojo <= '0';
wait for 80 ns;
infrarrojo <= '1'; -- Llega el 3 corredor
wait for 15 ns;
infrarrojo <= '0';
wait for 150 ns;
infrarrojo <= '1'; -- Llega el 4 corredor
wait for 15 ns;
infrarrojo <= '0';
wait;
end process;
end Behavioral;
xxxxxxxxxx
-------------------------------------------------------------------
-- Nombre: Breiner Castañeda Puentes / Natalia Duncan Altamar
-- Documento: 83235763 / 1001823843
-- Fecha: 10/12/2022
-- Proyecto: Fase Final
--------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Alto_nivel is
Port ( clk : in STD_LOGIC;
inicio : in STD_LOGIC;
reinicio : in STD_LOGIC;
infrarrojo : in STD_LOGIC;
Data_out : out STD_LOGIC_VECTOR (5 downto 0)
);
end Alto_nivel ;
architecture Behavioral of Alto_nivel is
component Cronometro
Port ( clk, inicio, reinicio : in STD_LOGIC;
Salida : out STD_LOGIC_VECTOR (5 downto 0)
);
end component;
component Memoria_RAM
port (CLK : in std_logic;
WE : in std_logic;
Direccion : in std_logic_vector(4 downto 0); -- Direccion de 6 bits
Dato_entrada : in std_logic_vector(5 downto 0); -- Entrada y
Dato_salida : out std_logic_vector(5 downto 0)
);
end component;
component interfaz
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
infrarrojo : in STD_LOGIC;
salida_enable : out std_logic;
Salida_interfaz: out STD_LOGIC_VECTOR (4 downto 0)
);
end component;
-- Señales internas
signal write_enable : STD_LOGIC:= '0';
signal Salida_cronometro : STD_LOGIC_VECTOR (5 downto 0):= (others => '0');
signal Salida_interfaz : STD_LOGIC_VECTOR (4 downto 0):= (others => '0');
begin
UO: Cronometro port map (
clk => clk,
inicio => inicio,
reinicio => reinicio,
Salida => Salida_cronometro
);
U1: Memoria_RAM port map (
clk => clk,
WE => write_enable,
Direccion => Salida_interfaz,
Dato_entrada => Salida_cronometro,
Dato_salida => Data_out
);
U3: interfaz port map (
clk => clk,
reset => reinicio,
infrarrojo => infrarrojo,
salida_enable => write_enable,
Salida_interfaz => Salida_interfaz
);
end Behavioral;
xxxxxxxxxx
-------------------------------------------------------------------
-- Nombre: Breiner Castañeda Puentes / Natalia Duncan Altamar
-- Documento: 83235763 / 1001823843
-- Fecha: 10/12/2022
-- Proyecto: Fase Final
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Memoria_RAM is
port (CLK : in std_logic;
WE : in std_logic;
Direccion : in std_logic_vector(4 downto 0);--Direccion de 6 bits
Dato_entrada : in std_logic_vector(5 downto 0);-- Entrada y -- Salidad de 6
Dato_salida : out std_logic_vector(5 downto 0)
);
end Memoria_RAM;
architecture Behavioral of Memoria_RAM is
type ram_type is array (31 downto 0) of std_logic_vector (5 downto 0);
signal My_RAM : ram_type;
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
if (WE = '1') then -- Write Enable : Escritura habilitada
My_RAM(to_integer(unsigned(Direccion))) <= Dato_entrada;
end if;
end if;
end process;
Dato_salida <= My_RAM(to_integer(unsigned(Direccion)));
end Behavioral;
xxxxxxxxxx
-------------------------------------------------------------------
-- Nombre: Breiner Castañeda Puentes / Natalia Duncan Altamar
-- Documento: 83235763 / 1001823843
-- Fecha: 10/12/2022
-- Proyecto: Fase Final
--------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity interfaz is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
infrarrojo : in STD_LOGIC;
salida_enable : out std_logic;
Salida_interfaz: out STD_LOGIC_VECTOR (4 downto 0)
);
end interfaz;
architecture Behavioral of interfaz is
signal Q00, D00, enable : std_logic := '0';
signal D11, Q11 : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
begin
process (clk)
begin
if clk'event and clk='1' then
if reset='1' then
Q00 <= '0';
else
Q00 <= D00;
end if;
end if;
end process;
D00 <= infrarrojo;
enable <= (not Q00) and D00;
salida_enable <= enable;
process (clk)
begin
if clk'event and clk='1' then
if reset='1' then
Q11 <= "00000";
elsif enable ='1' then
Q11 <= D11;
end if;
end if;
end process;
D11 <= "00000" when Q11 = 15 else
Q11 + 1;
Salida_interfaz <= Q11;
end Behavioral;
-------------------------------------------------------------------
-- Nombre: Breiner Castañeda Puentes / Natalia Duncan Altamar
-- Documento: 83235763 / 1001823843
-- Fecha: 10/12/2022
-- Proyecto: Fase Final
--------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Cronometro is
Port ( clk : in STD_LOGIC;
inicio : in STD_LOGIC;
reinicio : in STD_LOGIC;
Salida : out STD_LOGIC_VECTOR (5 downto 0)
);
end Cronometro;
architecture Behavioral of Cronometro is
signal D1, Q1, D2, Q2, D4, Q4, E2, R3 : std_logic;
signal D3, Q3 : STD_LOGIC_VECTOR (5 downto 0);
begin
process (clk)
begin
if clk'event and clk='1' then
if R3 ='1' then
Q3 <= "000000";
elsif Q2 ='1' then
Q3 <= D3;
end if;
end if;
end process;
D3 <= Q3 + 1;
process (clk)
begin
if clk'event and clk='1' then
if R3 ='1' then
Q2 <= '0';
elsif E2 ='1' then
Q2 <= D2;
end if;
end if;
end process;
D2 <= not Q2;
process (clk)
begin
if clk'event and clk='1' then
if R3 ='1' then
Q1 <= '0';
else
Q1 <= D1;
end if;
end if;
end process;
D1 <= inicio;
E2 <= inicio and (not Q1);
process (clk)
begin
if clk'event and clk='1' then
if reinicio ='1' then
Q4 <= '0';
else
Q4 <= D4;
end if;
end if;
end process;
D4 <= reinicio;
R3 <= reinicio and (not Q4);
Salida <= Q3;
end Behavioral;
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