Fase Final Electronica Digital(1) - EDA Playground
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Simulacion is
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--  
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end Simulacion;
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architecture Behavioral of Simulacion is
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component Alto_nivel 
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 Port ( clk         : in STD_LOGIC;
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        inicio      : in STD_LOGIC;
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        reinicio    : in STD_LOGIC;
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        infrarrojo  : in STD_LOGIC;
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        Data_out    : out STD_LOGIC_VECTOR (5 downto 0)
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);
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end component;
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-- Señales de las entradas
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signal clk, inicio, reinicio, infrarrojo : STD_LOGIC:=  '0';
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-- Señales de salidas
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signal Data_out : STD_LOGIC_VECTOR (5 downto 0):=  (others => '0');
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constant PERIOD : time := 10 ns; 
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begin
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process begin
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clk <= '0';
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wait for PERIOD/2;
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clk <= '1';
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wait for PERIOD/2;
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end process;
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UO: Alto_nivel port map (
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clk => clk,
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inicio  => inicio,
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reinicio  => reinicio,
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infrarrojo => infrarrojo,
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Data_out => Data_out
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);
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process begin
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--- Estímulos de la simulación wait for 100 ns;
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wait for 50 ns;
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--- Escribiendo en la memoria
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reinicio <= '1';
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wait for 50 ns;
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reinicio <= '0';
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wait for 150 ns;
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-- Empieza la carrera
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inicio <= '1';
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wait for 20 ns;
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inicio <= '0';
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wait for 520 ns;
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infrarrojo <= '1'; -- Llega el 1 corredor
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wait for 15 ns;
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infrarrojo <= '0';
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wait for 60 ns;
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infrarrojo <= '1'; -- Llega el 2 corredor
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wait for 15 ns;
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infrarrojo <= '0';
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wait for 80 ns;
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infrarrojo <= '1'; -- Llega el 3 corredor
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wait for 15 ns;
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infrarrojo <= '0';
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wait for 150 ns;
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infrarrojo <= '1'; -- Llega el 4 corredor
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wait for 15 ns;
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infrarrojo <= '0';
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wait;
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end process;
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end Behavioral;
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-------------------------------------------------------------------
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-- Nombre: Breiner Castañeda Puentes / Natalia Duncan Altamar
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-- Documento: 83235763 / 1001823843
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-- Fecha: 10/12/2022
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-- Proyecto: Fase Final
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--------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_unsigned.all;
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entity Cronometro is
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    Port ( clk      : in STD_LOGIC;
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           inicio   : in STD_LOGIC;
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           reinicio : in STD_LOGIC;
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           Salida : out STD_LOGIC_VECTOR (5 downto 0)
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);
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end Cronometro;
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architecture Behavioral of Cronometro is
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signal D1, Q1, D2, Q2, D4, Q4, E2, R3 : std_logic;
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signal D3, Q3 : STD_LOGIC_VECTOR (5 downto 0);
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begin
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process (clk)
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 begin
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    if clk'event and clk='1' then
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     if R3 ='1' then
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        Q3 <= "000000";
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     elsif Q2 ='1' then
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        Q3 <= D3;
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     end if;
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     end if;
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end process;
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D3 <= Q3 + 1;
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process (clk)
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begin
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   if clk'event and clk='1' then
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    if R3 ='1' then
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       Q2 <= '0';
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     elsif E2 ='1' then
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       Q2 <= D2;
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      end if;
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      end if;
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end process;
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D2 <= not Q2;
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process (clk)
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begin
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   if clk'event and clk='1' then
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    if R3 ='1' then
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       Q1 <= '0';
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     else
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       Q1 <= D1;
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     end if;
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     end if;
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end process;
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D1 <= inicio;
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E2 <= inicio and (not Q1);
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process (clk)
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begin
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     if clk'event and clk='1' then
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     if reinicio ='1' then
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        Q4 <= '0';
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      else
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        Q4 <= D4;
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     end if;
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     end if;
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end process;
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D4 <= reinicio;
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R3 <= reinicio and (not Q4);
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Salida <= Q3;
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end Behavioral;
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