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using EDA Playground
VHDL
Verilog/SystemVerilog
UVM
EasierUVM
SVAUnit
SVUnit
VUnit (Verilog/SV)
VUnit (VHDL)
TL-Verilog
e + Verilog
Python + Verilog
Python Only
C++/SystemC

205

 
//----------------------------------------------------------------------------------
//                      www.verificationguide.com
//----------------------------------------------------------------------------------
class sv_class;
  //class proporties
  int x;
  
  //method-1
  task set(int i);
    x = i;
  endtask
  
  //method-2
  function int get();
    return x;
  endfunction
  
endclass
  
module sv_class_ex;
 sv_class class_1;
  
  initial begin
    sv_class class_2 = new();
    class_1 = new();
    
    class_1.set(10);
    class_2.set(20);
    
    $display("\tclass_1 :: Value of x = %0d",class_1.get());
    $display("\tclass_2 :: Value of x = %0d",class_2.get());
  end
endmodule
​
​
  

design.sv

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