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module tb;
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reg clk_i;
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reg rst_i;
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reg data_i;
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wire pat_det_o;
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integer count;
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​
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pattern_det_mealy dut (.clk_i(clk_i),.rst_i(rst_i),.data_i(data_i),.pat_det_o(pat_det_o));
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​
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initial begin
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 clk_i=0;
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 forever #5 clk_i=~clk_i;
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end
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​
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initial begin
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 rst_i=1;
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 count=0;
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 data_i=0;
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#10;
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 rst_i=0;
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​
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  repeat(500)begin
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  @(posedge clk_i);
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    data_i=$random;
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end
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 // $display("number of times pattern detected=%d",count);
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#1000;
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  $display("number of times pattern detected=%d",count);
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$finish;
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end
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covergroup cg ;                         // @(posedge clk) as an event
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​
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​
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        option.per_instance = 1;
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​
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​
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             coverpoint dut.B            {
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                                            bins hig_input  = {1};
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                                         }
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​
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​
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             coverpoint dut.pat_det_o    {
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                                            bins low_output  = {0};
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                                            bins hig_output  = {1};
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                                         }
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​
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​
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​
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             coverpoint dut.state {
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                                    //when B=1 transition
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                                    bins trans_S_R_S_B      = (dut.S_R    => dut.S_B);
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                                    bins trans_S_B_S_BB     = (dut.S_B    => dut.S_BB);
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                                    bins trans_S_BB_S_BB    = (dut.S_BB   => dut.S_BB);
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                                    bins trans_S_BBC_S_BBCB = (dut.S_BBC  => dut.S_BBCB);
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                                    bins trans_S_BBCB_S_BB  = (dut.S_BBCB => dut.S_BB);
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​
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​
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                                  }
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endgroup
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​
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//cross  dut.B ,dut.state;
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           // cross between  i/p and PS
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​
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​
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​
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    covergroup cg1 ;                                                // @(posedge clk) as an event
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​
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        option.per_instance = 1;
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​
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​
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        coverpoint dut.B    {
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                               bins low_input  = {0};
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                            }
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​
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        coverpoint dut.state   { //when B!=0 Transaction
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​
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                                     bins trans_S_R_S_R    = (dut.S_R    => dut.S_R);                                                                         bins trans_S_B_S_R    = (dut.S_B    => dut.S_R);
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                                     bins trans_S_BB_S_BBC = (dut.S_BB   => dut.S_BBC);                                                                       bins trans_S_BBC_S_R  = (dut.S_BBC  => dut.S_R);
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                                     bins trans_S_BBCB_S_R = (dut.S_BBCB => dut.S_R);
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                                }
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​
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​
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        //cross dut.B,dut.state;                                                // cross between  i/p and PS
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​
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​
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    endgroup: cg1
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​
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​
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​
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    cg  cg_h;                                                               // instances of the covergroup
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    cg1 cg_h1;
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    initial begin: B2
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        cg_h  = new();
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        cg_h1 = new();
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      repeat(100)begin
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   #5;
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   cg_h.sample();
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   cg_h1.sample();
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  end
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​
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    end: B2
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​
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always@(posedge pat_det_o)begin
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 count=count+1;
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end
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  initial begin
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    $dumpvars();
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    $dumpfile("1.vcd");
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end
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​
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endmodule
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​
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​
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​
xxxxxxxxxx
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// Code your design here
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// Code your testbench here
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// or browse Examples
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module pattern_det_mealy(clk_i,rst_i,data_i,pat_det_o);
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​
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parameter S_R   = 5'b00001;
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parameter S_B   = 5'b00010;
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parameter S_BB  = 5'b00100;
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parameter S_BBC = 5'b01000;
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parameter S_BBCB= 5'b10000;
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​
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parameter B = 1'b1;
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parameter C = 1'b0;
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​
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input clk_i;
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input rst_i;
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input data_i;
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output reg pat_det_o;
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  reg [4:0] state,nextstate;
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​
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always@(posedge clk_i) begin
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if(rst_i==1) begin
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 pat_det_o=0;
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 state    =S_R;
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 nextstate=S_R;
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end
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else begin
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 case(state)
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​
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      S_R:begin
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         if(data_i==B)begin
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            pat_det_o=0;
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            nextstate=S_B;
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         end
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         else begin
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            pat_det_o=0;
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            nextstate=S_R;
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         end
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      end
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​
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      S_B:begin
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         if(data_i==B)begin
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            pat_det_o=0;
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            nextstate=S_BB;
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         end
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         else begin
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            pat_det_o=0;
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            nextstate=S_R;
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         end
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      end
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​
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      S_BB:begin
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         if(data_i==B)begin
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            pat_det_o=0;
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            nextstate=S_BB;
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         end
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         else begin
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            pat_det_o=0;
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            nextstate=S_BBC;
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         end
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      end
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​
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      S_BBC:begin
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         if(data_i==B)begin
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            pat_det_o=0;
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            nextstate=S_BBCB;
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         end
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         else begin
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            pat_det_o=0;
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            nextstate=S_R;
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         end
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      end
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​
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      S_BBCB:begin
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         if(data_i==B)begin
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            pat_det_o=1;
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            nextstate=S_BB;
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         end
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         else begin
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            pat_det_o=0;
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            nextstate=S_R;
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         end
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      end
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  endcase
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end
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end
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always@(nextstate)begin
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  state=nextstate;
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end
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endmodule
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