4-bit Adder - EDA Playground
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1
-- Alternative testbench
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library IEEE;
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use IEEE.std_logic_1164.all;
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​
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entity testbench2 is
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end testbench2;
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​
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architecture tb of testbench2 is
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​
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signal  x, y, z, sHA, cHA, sFA, cFA: std_logic;
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signal A, B, S: std_logic_vector (3 downto 0);
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signal C0, C4: std_logic;
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​
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begin
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​
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    DUT_HA: entity work.half_adder port map( x, y, sHA, cHA);
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    DUT_FA: entity work.full_adder port map( x, y, z, sFA, cFA);
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    DUT_Add4: entity work.adder_4bit(adder4_struct) port map( A, B, C0, S, C4);
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​
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    process begin
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​
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        x <= '0';
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        y <= '0';
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        z <= '0';
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        A <= "0000";
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        B <= "0000";
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        C0 <= '0';
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        wait for 10 ns;
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        assert (sHA='0' and cHA='0') report "ERROR Half adder on (0,0)";
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        assert (sFA='0' and cFA='0') report "ERROR Full adder on (0,0,0)";
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        assert (S="0000" and C4='0') report "ERROR  Adder 4 bit on (0000,0000,0)";
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        x <= '0';
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        y <= '1';
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        z <= '0';
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        A <= "0101";
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        B <= "1010";
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        C0 <= '0';
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        wait for 10 ns;
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        assert (sHA='1' and cHA='0') report "ERROR Half adder on (0,1)";
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        assert (sFA='1' and cFA='0') report "ERROR Full adder on (0,1,0)";
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        assert (S="1111" and C4='0') report "ERROR Adder 4 bit on (0101,1010,0)";
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​
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        x <= '1';
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        y <= '1';
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        z <= '0';
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        A <= "1100";
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        B <= "1001";
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        C0 <= '0';
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        wait for 10 ns;
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        assert (sHA='0' and cHA='1') report "ERROR Half adder on (1,1)";
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        assert (sFA='0' and cFA='1') report "ERROR Full adder on (1,1,0)";
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        assert (S="0101" and C4='1') report "ERROR Adder 4 bit on (1100,1001,0)";
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​
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        x <= '1';
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        y <= '1';
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        z <= '1';
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        A <= "1111";
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        B <= "0001";
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        C0 <= '0';
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        wait for 10 ns;
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        assert (sHA='0' and cHA='1') report "ERROR Half adder on (1,1)";
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        assert (sFA='1' and cFA='1') report "ERROR Full adder on (1,1,1)";
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        assert (S="0000" and C4='1') report "ERROR Adder 4 bit on (1111,0001,0)";
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    wait;
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    end process;
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​
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end tb; 
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1
-- 4-bit ripple carry adder with gerarchic dataflow-structural architecture and behavioral architecture
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​
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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​
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entity adder_4bit is
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    port ( A, B: in std_logic_vector(3 downto 0);  
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             C0: in std_logic;
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              S: out std_logic_vector(3 downto 0);
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             C4: out std_logic);
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end adder_4bit;
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​
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architecture adder4_struct of adder_4bit is
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​
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    signal C: std_logic_vector(4 downto 0);
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​
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begin
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    bit0: entity work.full_adder port map (A(0), B(0), C(0), S(0), C(1));
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    bit1: entity work.full_adder port map (A(1), B(1), C(1), S(1), C(2));
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    bit2: entity work.full_adder port map (A(2), B(2), C(2), S(2), C(3));
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    bit3: entity work.full_adder port map (A(3), B(3), C(3), S(3), C(4));
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    C(0) <= C0;
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    C4 <= C(4);
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end adder4_struct;
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​
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architecture adder4_beh of adder_4bit is
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​
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signal
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​
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    sum: std_logic_vector(4 downto 0);
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​
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begin
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    sum <= ('0' & A) + ('0' & B) + ("0000" & C0);
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    C4 <= sum(4);
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    S <= sum(3 downto 0);
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​
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end adder4_beh;
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4-bit ripple carry adder with two alternative testbenches

4-bit ripple carry adder with two alternative testbenches

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