Verilog: CMOS modeling - EDA Playground
Warning! This exercise has been opened in another tab; autosave has been disabled. Close this tab or refresh to reactivate.

 Languages & Libraries

 Tools & Simulators

 Examples

203


23
 
1
// Code your testbench here
2
// or browse Examples
3
​
4
module tb;
5
  reg d_in, p_ctrl, n_ctrl;
6
  wire out;
7
8
  cmos_modeling mos(d_in, p_ctrl, n_ctrl, out);
9
10
  initial begin
11
    $monitor("At time = %0d: d_in = %b, p_ctrl = %b, n_ctrl = %b, out = %b", $time, d_in, p_ctrl, n_ctrl, out);
12
  
13
    p_ctrl = 0; n_ctrl = 0; d_in = 0;
14
  
15
    #5 p_ctrl = 1;
16
    #5 d_in = 1;
17
    #5 d_in = 0;
18
​
19
    #5 n_ctrl = 1;
20
    #5 d_in = 1;
21
    #5 d_in = 0;
22
  end
23
endmodule
8
 
1
// Code your design here
2
module cmos_modeling (
3
  input d_in, p_ctrl, n_ctrl,
4
  output out);
5
6
  cmos p1(out, d_in, p_ctrl, n_ctrl);
7
8
endmodule
756 views and 0 likes     
 
Example for CMOS switch level modeling

Example for CMOS switch level modeling

160:0