t flip flop - EDA Playground
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module tb;
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    reg clk,rst,t;
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    wire q;
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    int delay;
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    t_ff DUT(.*);
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​
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    always #5 clk=~clk;
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    initial begin
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        rst=1; clk=0; t=0;
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    end
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    initial begin
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        @(posedge clk) rst=0;
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        for(int i=0;i<20;i++)
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            begin
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                delay=$urandom_range(3,7);
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                t=~t;
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                #delay;
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            end
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        #20 $finish;
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    end
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    initial begin
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        $dumpfile("file1.vcd");
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        $dumpvars(1,tb);
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    end
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endmodule
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​
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// Code your design here
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module t_ff(clk,
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            rst,
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            t,
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            q
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            );
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    input clk,rst,t;
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    output reg q;
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​
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    always@(posedge clk or posedge rst)
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        begin
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            if(rst==1'b1)
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                q<=0;
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            else
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            begin
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                if(t==1'b0)
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                    q<=q;
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                else
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                    q<=~q;
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            end
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        end
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​
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endmodule
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