SystemVerilog for loop - EDA Playground
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module tb;
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    initial begin
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      // This for loop increments i from 0 to 9 and exit
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      for (int i = 0 ; i < 10; i++) begin
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        // Let's create a condition such that the
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        // for loop
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        if (i == 7)
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          continue;
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        $display ("Iteration [%0d]", i);
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      end
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    end
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endmodule
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/*
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Simulation Log:
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---------------
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​
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ncsim> run
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Iteration [0]
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Iteration [1]
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Iteration [2]
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Iteration [3]
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Iteration [4]
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Iteration [5]
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Iteration [6]
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Iteration [8]
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Iteration [9]
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ncsim: *W,RNQUIE: Simulation is complete.
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ncsim> exit
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*/
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