Why bother with packages in SystemVerilog? - EDA Playground
Warning! This exercise has been opened in another tab; autosave has been disabled. Close this tab or refresh to reactivate.

 Languages & Libraries

 Tools & Simulators

 Examples

202


14
 
1
​
2
module M;
3
4
  initial begin
5
    static P1::medal m1;
6
    static P2::metal m2;
7
    $display("m1= %b", m1);
8
    m1 = P1::BRONZE;
9
    m2 = P2::BRONZE;
10
    $display("m1= %b", m1);
11
  end
12
13
endmodule
14
​
10
 
1
​
2
package P1;
3
  typedef enum logic[1:0] {BRONZE, SILVER, GOLD} medal;
4
endpackage
5
​
6
package P2;
7
  typedef enum logic[1:0] {BRONZE, SILVER, GOLD} metal;
8
endpackage
9
​
10
​
286 views and 0 likes     
 
In SystemVerilog you are not allowed to use the same value for two different enums in the same scope. For example, this is not allowed:
​
  
````
typedef enum logic[1:0] {BRONZE, SILVER, GOLD} medal;
typedef enum logic[1:0] {BRONZE, SILVER, GOLD} metal;
````
​
So, what to do?
​
​
A SystemVerilog package is a scope. It has a name. That's the whole point of it. We can declare our two enums in different packages:
​
````
package P1;
  typedef enum logic[1:0] {BRONZE, SILVER, GOLD} medal;
endpackage
​
package P2;
  typedef enum logic[1:0] {BRONZE, SILVER, GOLD} metal;
endpackage
````
​
so now, they are in different scopes. As long as we don't try to import everything in each package into the same scope, in other words, as long as we don't do this:
​
​
````
import P1::*;
import P2::*; 
````
​
but instead refer to each enum type and value using the scope resolution operator - `::` - then we're OK. This is a good illustration of the whole point of having packages in SystemVerilog.

In SystemVerilog you are not allowed to use the same value for two different enums in the same scope. For example, this is not allowed:

typedef enum logic[1:0] {BRONZE, SILVER, GOLD} medal;
typedef enum logic[1:0] {BRONZE, SILVER, GOLD} metal;

So, what to do?

A SystemVerilog package is a scope. It has a name. That's the whole point of it. We can declare our two enums in different packages:

package P1;
  typedef enum logic[1:0] {BRONZE, SILVER, GOLD} medal;
endpackage

package P2;
  typedef enum logic[1:0] {BRONZE, SILVER, GOLD} metal;
endpackage

so now, they are in different scopes. As long as we don't try to import everything in each package into the same scope, in other words, as long as we don't do this:

import P1::*;
import P2::*;

but instead refer to each enum type and value using the scope resolution operator - :: - then we're OK. This is a good illustration of the whole point of having packages in SystemVerilog.

321680:0