mealy sequence detector 0010 - EDA Playground
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// Code your testbench here
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// or browse Examples
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module tb();
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  reg clk,rst,in;
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  wire out;
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  mealy_sd m1(clk,rst,in,out);
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  initial begin
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    clk = 0;
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    forever #5 clk = ~clk;
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  end
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  initial begin
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    in = 0;
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    rst = 1;
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    #30 rst = 0;
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    #10 in = 1;
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    #10 in = 0;
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    #10 in = 0;
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    #10 in = 0;
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    #10 in = 0;
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    #10 in = 0;
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    #10 in = 1;
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    #10 in = 0;
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    #100 $finish;
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  end
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  initial begin
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    $dumpfile("dump.vcd");
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    $dumpvars;
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  end
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endmodule
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65
 
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// Code your design here
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module mealy_sd(clk,rst,in,out);
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  input clk,rst,in;
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  output reg out;
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  //reg y;
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  parameter A = 2'b00;
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  parameter B = 2'b01;
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  parameter C = 2'b10;
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  parameter D = 2'b11;
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  reg [2:0] state, nxt_state;
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  always@(posedge clk , posedge rst) begin
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    if(rst == 1) begin
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      state <= A;
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      out <= 0;
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    end
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    else begin
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      state <= nxt_state;
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      //out <= y;
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    end
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  end
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  always@(state) begin
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    case(state)
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      A : begin
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        if(in == 0) begin
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          nxt_state <= B;
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          out <= 0;
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        end else begin
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          nxt_state <= A;
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          out <= 0;
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        end
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      end
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      B : begin
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        if(in == 0) begin
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          nxt_state <= C;
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          out <= 0;
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        end else begin
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          nxt_state <= A;
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          out <= 0;
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        end
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      end
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      C : begin
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        if(in == 0) begin
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          nxt_state <= C;
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          out <= 0;
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        end else begin
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          nxt_state <= D;
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          out <= 0;
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        end
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      end
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      D : begin
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        if(in == 0) begin
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          nxt_state <= B;
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          out <= 1;
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        end else begin
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          nxt_state <= A;
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          out <= 0;
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        end
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      end
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      default : begin
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        nxt_state <= A;
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        out <= 0;
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      end
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    endcase
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  end
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endmodule
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