TLM-4 - EDA Playground
Warning! This exercise has been opened in another tab; autosave has been disabled. Close this tab or refresh to reactivate.

 Languages & Libraries

 Tools & Simulators

 Examples

204


39
 
1
//-------------------------------------------
2
//      www.verificationguide.com 
3
//-------------------------------------------
4
5
class component_a extends uvm_component;
6
  
7
  transaction trans;
8
  uvm_blocking_put_port#(transaction) trans_out; 
9
  
10
  `uvm_component_utils(component_a)
11
  
12
  //--------------------------------------- 
13
  // Constructor
14
  //---------------------------------------
15
  function new(string name, uvm_component parent);
16
    super.new(name, parent);
17
    trans_out = new("trans_out", this); 
18
  endfunction : new
19
20
  //---------------------------------------
21
  // run_phase 
22
  //---------------------------------------
23
  virtual task run_phase(uvm_phase phase);
24
    phase.raise_objection(this);
25
    
26
    trans = transaction::type_id::create("trans", this);
27
28
    void'(trans.randomize());
29
    `uvm_info(get_type_name(),$sformatf(" tranaction randomized"),UVM_LOW)
30
    `uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
31
    
32
    `uvm_info(get_type_name(),$sformatf(" Before calling port put method"),UVM_LOW)
33
    trans_out.put(trans);
34
    `uvm_info(get_type_name(),$sformatf(" After  calling port put method"),UVM_LOW)
35
    
36
    phase.drop_objection(this);
37
  endtask : run_phase
38
39
endclass : component_a
xxxxxxxxxx
1
 
1
922 views and 1 likes     
 
www.verificationguide.com

www.verificationguide.com

130:0