Verilog bit change location

Languages & Libraries

Testbench + Design

UVM / OVM

Other Libraries

Enable TL-Verilog

Enable Easier UVM

Enable VUnit

Examples

using EDA Playground
VHDL
Verilog/SystemVerilog
UVM
EasierUVM
SVAUnit
SVUnit
VUnit (Verilog/SV)
VUnit (VHDL)
TL-Verilog
e + Verilog
Python + Verilog
Python Only
C++/SystemC

208

 
// Code your testbench here
module test;
  logic [15:0]  my_reg1=16'b0001011011010111, 
                my_reg2=16'b1111011011010111, 
                my_reg1_diff, my_reg2_diff;
  integer my_reg1_diff_pos, my_reg2_diff_pos;
​
//Synthesizable Implementation of floor of log2 function:
function integer flog2;
  input [31:0] value;
  integer i;
  for (i=31; i>=0; i--)
    if (value[i]) return i;
endfunction
​
  
  always_comb begin
    my_reg1_diff = (my_reg1 ^ (my_reg1 << 1))>>1 ;
    my_reg2_diff = (my_reg2 ^ (my_reg2 << 1))>>1 ;
    my_reg1_diff_pos = flog2(my_reg1_diff);             //floor of log2 of my_reg1_diff (Synthesizable version)
    my_reg2_diff_pos = $floor($ln(my_reg2_diff)/$ln(2));//floor of log2 of my_reg2_diff
    
  end
  
  initial begin
    $monitor ("my_reg1_diff=%b, my_reg1_diff_pos=%d, my_reg2_diff=%b, my_reg2_diff_pos=%d", 
                my_reg1_diff, my_reg1_diff_pos, 
                my_reg2_diff, my_reg2_diff_pos);
    #100 $finish;
  end
  
  
​
endmodule
​

design.sv

xxxxxxxxxx
 
// Code your design here
​

Languages & Libraries

Tools & Simulators

Examples