| Name | Description | User | Modified | Likes | Views |
|---|---|---|---|---|---|
| VHDL - Basic OR Gate | Simple VHDL example of an OR gate design and testbench. | Victor Lyuboslavsky | 2019/10/28 4:05pm | 222 | 235494 |
| RAM | Random Access Memory example and testbench | Victor Lyuboslavsky | 2019/10/28 4:05pm | 11 | 25748 |
| Minimum and Maximum Example | # Minimum and Maximum Example In VHDL 2008 there are two built-in functions MAXIMUM and MINIMUM tha... | Doulos Example | 2019/10/28 4:06pm | 4 | 24367 |
| If Example | # If Example An `if` statement is a sequential statement which executes one branch from a set of br... | Doulos Example | 2019/10/28 4:06pm | 6 | 13554 |
| VHDL Precision example | Here is a simple example of running the Mentor Precision synthesizer. (Because of the way EDA Pla... | Doulos Example | 2020/11/02 11:39am | 2 | 13376 |
| Port Map Example | # Port Map Example A port map is typically used to define the interconnection between instances in ... | Doulos Example | 2019/10/28 4:06pm | 2 | 11836 |
| Direct and Component Instantiation Example | # Direct and Component Instantiation Example VHDL-93 and later offers two methods of _instantiation... | Doulos Example | 2019/10/28 4:06pm | 1 | 8762 |
| Generic Package Example | # Generic Package Example A package contains common definitions that can be shared across a VHDL de... | Doulos Example | 2019/10/28 4:06pm | 0 | 8596 |
| Array Example | # Array Example A VHDL array is a data type which consists of a vector or a multi-dimensional set o... | Doulos Example | 2019/10/28 4:06pm | 1 | 8534 |
| For Loop Example | # For Loop Example A foor loop is a sequential statement used to execute a set of sequential statem... | Doulos Example | 2019/10/28 4:06pm | 2 | 8115 |
| how to use run.do with VHDL | An example run.do file for each of the commercial simulators. In each case, code is necessary to sav... | Doulos Example | 2020/11/02 2:49pm | 2 | 7693 |
| Alias Example | # Alias Example A VHDL alias lets you give an alternative name for almost anything. They are partic... | Doulos Example | 2019/10/28 4:06pm | 0 | 7538 |
| Generate Example | # Generate Example A generate statement is a concurrent statement used to create regular structures... | Doulos Example | 2019/10/28 4:06pm | 1 | 7039 |
| TextIO Write Example | # TextIO Write Example `TEXTIO` is a VHDL package which allows the reading and writing of ASCII tex... | Doulos Example | 2019/10/28 4:06pm | 1 | 6474 |
| External Name Example | # External Name Example VHDL 2008 adds external names to allow hierarchical access to objects that ... | Doulos Example | 2019/10/28 4:06pm | 0 | 5807 |
| TextIO Read Example | # TextIO Read Example `TEXTIO` is a VHDL package which allows the reading and writing of ASCII text... | Doulos Example | 2019/10/28 4:06pm | 0 | 5226 |
| Signal Example | # Signal Example A `signal` represents an electrical connection, wire or bus. Signals are used for ... | Doulos Example | 2019/10/28 4:06pm | 0 | 4927 |
| OSVVM Example | Simple example of functional coverage using CoveragePkg of OSVVM | Victor Lyuboslavsky | 2019/10/28 4:05pm | 3 | 4849 |
| Access Type Example | # Access Type An *access type* is a data type which allows dynamic memory allocation, equivalent to... | Doulos Example | 2019/10/28 4:06pm | 2 | 4655 |
| Entity Example | # Entity Example An Entity defines the interface to a hierarchical block. An entity is used in comb... | Doulos Example | 2019/10/28 4:06pm | 1 | 4589 |
| Generic Example | # Generic Example Generics are used to parameterize a design entity. Different Instances of the sam... | Doulos Example | 2019/10/28 4:06pm | 0 | 4500 |
| Floating Example | # Floating Example A data type representing an abstraction of a mathematical floating point number.... | Doulos Example | 2019/10/28 4:06pm | 0 | 4321 |
| Shared Variable and Protected Type Example | # Shared Variable and Protected Type Example A `shared variable` is a `variable` that can be declar... | Doulos Example | 2019/10/28 4:06pm | 0 | 4296 |
| Assert Example | # Assert Example An assert statement is a sequential or concurrent statement used to write out a me... | Doulos Example | 2019/10/28 4:06pm | 1 | 4248 |
| Procedure Example | # Procedure Example A `procedure` is used to group together executable, sequential statements. A pr... | Doulos Example | 2019/10/28 4:06pm | 0 | 4193 |
| VHDL-2019 std.env | This example shows some of the new features of the std.env package. (The ones supported by Riviera P... | Doulos Example | 2020/08/22 12:27pm | 0 | 3931 |
| Wait Example | # Wait Example A `wait` statement is a sequential statement which waits for an event on a signal in... | Doulos Example | 2019/10/28 4:06pm | 1 | 3891 |
| Numeric Std Example | # Numeric Std Example `NUMERIC_STD` is an IEEE standard package that defines arithmetic operations ... | Doulos Example | 2017/06/23 2:38pm | 2 | 3858 |
| While Loop Example | # While Loop Example A `while loop` is a sequential statement. The statements inside the while loop... | Doulos Example | 2019/10/28 4:06pm | 1 | 3672 |
| Architecture Example | # Architecture Example A VHDL architecture defines the internal view of a block of hardware, i.e. t... | Doulos Example | 2019/10/28 4:06pm | 0 | 3619 |
| Process Example | # Process Example One of the aims of an HDL is to express the function of the HW block in a more co... | Doulos Example | 2019/10/28 4:06pm | 1 | 3547 |
| Configuration and Context Example | # Configuration and Context Example ## Context (VHDL 2008) A context is used to define a set of li... | Doulos Example | 2019/10/28 4:06pm | 0 | 3541 |
| Aggregate Example | # Aggregate Example An aggregate is a way to write a value for any array or record. An aggregate is... | Doulos Example | 2019/10/28 4:06pm | 1 | 3517 |
| Case Example | # Case Example A VHDL case statement is a sequential statement which conditionally executes one bra... | Doulos Example | 2019/10/28 4:06pm | 1 | 3178 |
| Function Example | # Function Example A function is used to group together executable, sequential statements to define... | Doulos Example | 2019/10/28 4:06pm | 0 | 3137 |
| File Example | # File Example A file is a stream of values of a specified type which can be read or written during... | Doulos Example | 2019/10/28 4:06pm | 1 | 3030 |
| Block Example | # Block Example A VHDL block statement is a concurrent statement used to group together concurrent ... | Doulos Example | 2019/10/28 4:06pm | 0 | 2498 |
| VHDL 2008 Port Map Example | # Port Map Example A port map is typically used to define the interconnection between instances in ... | Doulos Example | 2019/10/28 4:06pm | 0 | 2478 |
| Package Example | # Package Example A `package` contains common definitions that can be shared across a VHDL design o... | Doulos Example | 2019/10/28 4:06pm | 1 | 2309 |
| Generic Map Example | # Generic Map Example Generic maps are used to define the values of generics. Usually given in an I... | Doulos Example | 2019/10/28 4:06pm | 0 | 2294 |
| Variable Example | # Variable Example A variable stores a value within a process. A variable must be declared within t... | Doulos Example | 2019/10/28 4:06pm | 1 | 2244 |
| Record Example | # Record Example A `record` type is a data type that represents a set of values of different types.... | Doulos Example | 2019/10/28 4:06pm | 0 | 2135 |
| Integer Example | # Integer Example An INTEGER type represents a mathematical integer. The maximum values for the ran... | Doulos Example | 2019/10/28 4:06pm | 0 | 2116 |
| Loop Example | # Loop Example A `loop` statement is a sequential statement used to execute a set of sequential sta... | Doulos Example | 2019/10/28 4:06pm | 1 | 2074 |
| Select Example | # Select Example The `select` statement is a concurrent statement which assigns one of several expr... | Doulos Example | 2019/10/28 4:06pm | 1 | 2055 |
| Aldec HES-SynHESer demo | Here is an example of using Aldec HES-SyntHESer. Here are some key points: 1. It looks for a tab ca... | EDA Playground | 2024/12/23 3:23pm | 2 | 1919 |
| VHDL-2019 private and alas in protected types | From the Aldec Riviera Pro 2020.04 release notes: [In VHDL-2019] Aliases and variables are allowe... | Doulos Example | 2020/08/22 12:32pm | 0 | 1833 |
| Configuration Specification Example | # Configuration Specification Example A configuration specification defines which entity and archit... | Doulos Example | 2019/10/28 4:06pm | 0 | 1821 |
| User-Defined Attribute Example | # User-Defined Attribute Example A user defined attribute is used to attach arbitrary information t... | Doulos Example | 2019/10/28 4:06pm | 0 | 1812 |
| Generic 2008 Example | # VHDL-2008 Generic Example Generics are used to parameterize a design entity. Different Instances ... | Doulos Example | 2019/10/28 4:06pm | 1 | 1807 |
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