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using EDA Playground
VHDL
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C++/SystemC

208

 
module EX_procedural_assignment2;
​
  byte unsigned count, value;
​
  initial begin
    // At time 2, evaluate RHS and schedule assignment for 1 time slot
    // later - LHS changes at time 3
    #2 value <= #1  count;
  
    // 6 time steps later (time 8), evaluate RHS and schedule assignment
    // for 3 time slots further on (time 11)
    #6 value <= #3  count;
  end
​
  initial begin
    // blocking assignment of RHS at time 5
    #5 value  =     count;  
  
    // at time 6, evaluate the RHS and schedule the assignment for 
    // the NBA region 7 time slots later (time 13)
    #1 value <= #7  count;
  
    // at time 10, evaluate the RHS and schedule the assignment for 
    // the active region 3 time slots later (time 13)
    #4 value  = #3  count; 
  
    // the NB assignment 'wins' because the NBA region occurs after 
    // the active region in the time step.
    #10 $stop;
  end
​
  assign #1 count = count + 1;
​
  always @(value) $display("%4t: Value = %0d", $time, value);
​
endmodule

design.sv

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// Code your design here
​

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