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// Example of delay issues
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`default_nettype none
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​
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module delayinv(input a, output reg z);
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​
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  always @(a)
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    z<=#5 ~a;
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​
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endmodule
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module delayand(input a, input b, output reg z);
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  always @(a,b)
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     z<=#5 a&b;
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endmodule
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​
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module test;
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reg a, b;
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wire anot, z;
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​
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​
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reg aff, bff, zff;
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reg clk;
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​
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  delayinv gate1(aff,anot);
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  delayand gate2(anot,bff,z);
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​
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always
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  #10 clk=~clk;
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​
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// input flip flop A
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  always @(posedge clk)
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     aff<=a;
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​
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// input flip flop B
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  always @(posedge clk)
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    bff<=b;
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​
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// output flip flop
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  always @(posedge clk)
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   zff<=z;
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​
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initial
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  begin
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    // Dump waves
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    $dumpfile("dump.vcd");
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    $dumpvars(1);
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    a=1'b0;
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    b=1'b0;
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    clk=1'b0;
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​
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#15  b=1'b1;
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    a=1'b1;
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#145 b=1'b0;
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    $finish;
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  end
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​
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​
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endmodule
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