Edit code - EDA Playground
Warning! This exercise has been opened in another tab; autosave has been disabled. Close this tab or refresh to reactivate.

 Languages & Libraries

 Tools & Simulators

 Examples

203


34
 
1
// Code your testbench here
2
// or browse Examples
3
4
module testbench;
5
  reg clk, up_down, reset;
6
  wire [3:0] out;
7
  
8
  up_down_4bitcounter
9
  dut (.out(out),
10
       .clk(clk),
11
       .reset(reset),
12
       .up_down(up_down)
13
       );
14
  
15
  // Need that for plotting
16
  initial begin
17
    $dumpfile("dump.vcd");
18
    $dumpvars;
19
  end
20
  
21
  initial begin
22
    clk = 0;
23
    reset = 0;
24
    up_down = 1;
25
    #10 reset = 1;
26
    #10 reset = 0;
27
    #100 $finish;
28
  end
29
  
30
  always begin
31
    #1 clk = ~clk;
32
  end
33
  
34
endmodule
29
 
1
module up_down_4bitcounter (
2
out,
3
up_down,
4
clk,
5
data,
6
reset
7
);
8
9
//Output Ports
10
output [3:0] out;
11
12
//Input Ports
13
input [3:0] data;
14
input up_down, clk, reset;
15
16
//Internal Variables
17
reg [3:0] out;
18
19
//Start of Code
20
always @(negedge clk)
21
if (reset) begin // active high reset
22
out <= 4'b0 ;
23
end else if (up_down) begin
24
out <= out + 1;
25
end else begin
26
out <= out - 1;
27
end
28
29
endmodule 
202 views and 0 likes     
A short description will be helpful for you to remember your playground's details
 
100:0