stackoverflow 28710323 - EDA Playground
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// Code your testbench here
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// or browse Examples
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module propagateEvents;
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reg clk;
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event trig;
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initial
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begin
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    clk = 1'b0;
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end
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always #10 clk = ~clk;
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eventGen eventGen (trig, clk);
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eventConsume eventConsume (trig, clk);
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  initial begin
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    repeat(5) @(trig);
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    @(posedge clk) #1;
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    $finish;
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  end
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endmodule
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// Code your design here
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module eventGen(output event trigGen, input clk);
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  reg [3:0] count;
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initial
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    count = 0;
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always @(posedge clk)
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begin
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    count = count + 1'b1;
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    if (count == 'h8)
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        ->trigGen;
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end
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endmodule
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module eventConsume(input event trigConsume, input clk);
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always @(trigConsume)
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begin
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    $display("Trigger caught");
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end
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endmodule
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http://stackoverflow.com/questions/28710323/in-systemverilog-can-events-be-defined-in-ports
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