check pci monclk sv (wrong result) - EDA Playground
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// or browse Examples
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// or browse Examples
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`timescale 1ns/1ns
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`include "slv_pci.v"
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`include "slv_pci_shell.sv"
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`include "pci_bus_if.sv"
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//`include "test_uvm.sv"
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//`timescale 1ns/1ns
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// use parameter to allow changes by higher design module
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parameter IO_Address = 32'h0000_0200;
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parameter ADDRMASK = 32'hFFFF_FFF0;  // remove A<3:0>
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parameter IO_Read_CMD = 4'h2;
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parameter IO_Write_CMD = 4'h3;
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parameter      AREG_WIDTH = 2;    // 2 address bits for 4 data registers
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parameter      DREG_DEPTH = 4;    // 4 data register 
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parameter      WAIT_WIDTH = 3;    // wait 2^3 -1 = 7
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module test_uvm (interface.port_test   bus);
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integer wr_data;
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integer rd_data;
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integer address, data;
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logic   write;
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   initial begin
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     wr_data = 12;
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     single_reset ();
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     fork
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        begin
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          single_write_drv_uvm (.address (32'h0000_0204),.data (wr_data));
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           single_read_drv_uvm (.address (32'h0000_0204),.data (rd_data));
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        end
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        begin
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           get_item_mon_uvm (.address (address), .write (write),.data (data));
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          if (address == 32'h0000_0204) $display ("Correct address\n");
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            else              $display ("Incorrect address\n");
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          if (write   == 1) $display ("Correct type\n");
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            else              $display ("Incorrect type\n");
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          if (data    == wr_data) $display ("Correct write data\n");
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            else              $display ("Incorrect write data\n");
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          $display ("Expect data: time=%t  address = %0h, write mode = %s, data = %d\n", $time, 32'h0000_0204, "true", wr_data); 
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          $display ("Mon: time=%t  address = %0h, write mode = %s, data = %d\n", $time, address, ((write) ? "true" : "false"), data); 
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           get_item_mon_uvm (.address (address), .write (write),.data (data));     
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          if (address == 32'h0000_0204) $display ("Correct address\n");
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            else              $display ("Incorrect address\n");
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          if (write   == 0) $display ("Correct type\n");
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            else              $display ("Incorrect type\n");
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          if (data    == wr_data) $display ("Correct write data\n");
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            else              $display ("Incorrect write data\n");
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          $display ("Expect data: time=%t  address = %0h, write mode = %s, data = %d\n", $time, 32'h0000_0204, "false", wr_data); 
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           $display ("Mon: time=%t  address = %0h, write mode = %s, data = %d\n", $time, address, ((write) ? "true" : "false"), data); 
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        end
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     join
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     $100;
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     if (rd_data == wr_data) 
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         $display ("Pass matched: wr_data = %d, rd_data = %d\n",wr_data, rd_data, wr_data);
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     else
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         $display ("Fail mismatched: wr_data = %d, rd_data = %d\n",wr_data, rd_data, wr_data);
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     #10 $finish;     
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   end          
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//   `include"single_reset.sv"
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task single_reset;
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   //input integer address;
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   //output integer data;
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   // Comment: Test pass case for Single Read Cycle for all assertion checks
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   // Comment: PCI waveform signal changes at the falling clock edge.
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   //   CLK        :_/~\_/~\_/~\
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   //   RSTn       :________~~~~
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   //   FRAMEn     :~~~~~~~~~~~~
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   //   ADm        :< 0>< 0>< 0>
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   //   OE_ADm     :~~~~~~~~~~~~
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   //   CBEn       :< 0>< 0>< 0>
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   //   IRDYn      :~~~~~~~~~~~~
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   //   TRDYn      :~~~~~~~~~~~~
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   //   DEVSELn    :~~~~~~~~~~~~
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   //   waitdelay  :< 0>< 0>< 0>
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   @(bus.DRVCLK); // Cycle 0
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   bus.DRVCLK.RSTn   <= 1'b0;
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   bus.DRVCLK.FRAMEn <= 1'b1;
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   bus.DRVCLK.AD     <= 32'h0000_0000;
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   //ADm        <= 32'h0000_0000;
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   //OE_ADm     <= 1'b1;
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   bus.DRVCLK.CBEn   <= 4'h0;
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   bus.DRVCLK.IRDYn  <= 1'b1;
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   bus.DRVCLK.waitdelay <= 4'h0;
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   @(bus.DRVCLK); // Cycle 0
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   bus.DRVCLK.RSTn   <= 1'b0;
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   bus.DRVCLK.FRAMEn <= 1'b1;
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   bus.DRVCLK.AD        <= 32'h0000_0000;
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   //ADm        <= 32'h0000_0000;
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   //OE_ADm     <= 1'b1;
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   bus.DRVCLK.CBEn   <= 4'h0;
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   bus.DRVCLK.IRDYn  <= 1'b1;
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   bus.DRVCLK.waitdelay <= 4'h0;
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   @(bus.DRVCLK); // Cycle 0
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   bus.DRVCLK.RSTn   <= 1'b1;
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   bus.DRVCLK.FRAMEn <= 1'b1;
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   bus.DRVCLK.AD     <= 32'h0000_0000;
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   //ADm        <= 32'h0000_0000;
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   //OE_ADm     <= 1'b1;
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   bus.DRVCLK.CBEn   <= 4'h0;
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   bus.DRVCLK.IRDYn  <= 1'b1;
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   bus.DRVCLK.waitdelay <= 4'h0;
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endtask
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  `include"single_write_drv_uvm.sv"
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   `include"single_read_drv_uvm.sv"
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   `include"get_item_mon_uvm.sv"
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   `include"get_write_mon_uvm.sv"
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   `include"get_read_mon_uvm.sv"
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endmodule
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module testbench;
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    //  signal declaration //
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    bit CLK;
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    //  Module declaration //
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    pci_bus_if       bus      (CLK);
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    slv_pci_shell    dut      (bus.port_dut);
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    test_uvm         test     (bus.port_test);
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    //  clock generation   //
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    initial forever #(10/2) CLK = ~CLK;
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    //initial $dumpvars(0, testbench);
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    initial $dumpvars(0, testbench.bus);
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    initial $dumpvars(0, testbench.test);
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    initial $dumpvars(0, testbench.dut.dut);
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endmodule
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  // 12-15 version
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  task single_read_drv_uvm;
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   input integer address;
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   output integer data;
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      // Comment: Test pass case for Single Read Cycle for all assertion checks
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      // Comment: PCI waveform signal changes at the falling clock edge.
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      //   CLK        :_/~\_/~\_/~\_/~\_/~\
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      //   FRAMEn     :~~~~____~~~~~~~~~~~~
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      //   AD         :< 0>< A>< z>< z>< D>
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      //   CBEn       :< 0>< C>< F>< F>< 0>
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      //   IRDYn      :~~~~~~~~________~~~~
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      //   TRDYn      :~~~~~~~~~~~~____~~~~
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      //   DEVSELn    :~~~~~~~~________~~~~
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      @(bus.DRVCLK); // Cycle 0
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      bus.DRVCLK.FRAMEn     <= 1'b1;
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      bus.DRVCLK.AD         <= 32'h0000_0000;
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      bus.DRVCLK.CBEn       <= 4'h0;
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      bus.DRVCLK.IRDYn      <= 1'b1;
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      @(bus.DRVCLK); // Cycle 1
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      bus.DRVCLK.FRAMEn     <= 1'b0;
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      //bus.DRVCLK.AD         <= req.address + IO_Address;
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      //bus.DRVCLK.AD         <= address + IO_Address;
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      bus.DRVCLK.AD         <= address;
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      bus.DRVCLK.CBEn       <= IO_Read_CMD;
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      bus.DRVCLK.IRDYn      <= 1'b1;
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      @(bus.DRVCLK); // Cycle 2
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      bus.DRVCLK.FRAMEn     <= 1'b1;
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      bus.DRVCLK.AD         <=  'hz;
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      bus.DRVCLK.CBEn       <= 4'hF;
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      bus.DRVCLK.IRDYn      <= 1'b0;
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      @(bus.DRVCLK); // Cycle 3
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      bus.DRVCLK.FRAMEn     <= 1'b1;
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      bus.DRVCLK.AD         <=  'hz;
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      bus.DRVCLK.CBEn       <= 4'hF;
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      bus.DRVCLK.IRDYn      <= 1'b0;
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      @(bus.DRVCLK); // Cycle 4
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      bus.DRVCLK.FRAMEn     <= 1'b1;
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      //req.data = bus.DRVCLK.AD;
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      data = bus.DRVCLK.AD;
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      bus.DRVCLK.CBEn       <= 4'h0;
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      bus.DRVCLK.IRDYn      <= 1'b1;
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   endtask
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