SystemVerilog Enumerated Type conversion

SystemVerilog Enumerated Type conversion - EDA Playground

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testbench.sv

 
// Code your testbench here
// or browse Examples
​
module enum_method; 
  typedef enum {RED, BLUE, GREEN} COLOR_E;
  COLOR_E color, c2;
  integer c;
  initial begin
    c = color; // Convert from enum to integer
    c++; // Increment integer
    if (!$cast(color, c)) begin // Cast integer back to enum
      $display("Cast failed for c=%0d", c);
    end
    $display("Color is %0d & %0s", color, color.name);
    c2 = COLOR_E'(c); // No type checking done
  end
​
endmodule 

design.sv

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// Code your design here
​

Languages & Libraries

Tools & Simulators

Examples

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None
OVL
SVUnit
SVAUnit 3.0
ClueLib 0.6.1
svlib 0.5

None
OVL
OSVVM
UVVM

None
SystemC 2.3.3