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package my_package;
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class Register;
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  // Properties
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  logic [7:0] data;
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  // Methods
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  function new (logic[7:0] d = 0); // Constructor
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    data = d;
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  endfunction
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  task load (logic[7:0] d);
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    data = d;
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  endtask
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endclass
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// Parameterised classes
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class Register1 #(parameter n = 8);
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  logic [n-1:0] data;
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endclass
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class Register2 #(parameter type T);
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  T data;
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endclass
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// Derived class
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class ShiftRegister extends Register;
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  extern task shiftleft();
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  extern task shiftright();
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endclass
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// Out of class method definitions
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task ShiftRegister::shiftleft();
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  data = data << 1;
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endtask
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task ShiftRegister::shiftright();
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  data = data >> 1;
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endtask
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endpackage
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module GRG_class1;
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import my_package::*;
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Register accum; // accum stores a handle to an object of class Register
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Register1 #(8) accum1_8 = new;           // 8-bit register
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Register1 #(.n(16)) accum1_16 = new;     // 16-bit register
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Register2 #(int) accum2_8 = new;         // int register
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Register2 #(bit [7:0]) accum2_16 = new;  // bit[7:0] register
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ShiftRegister SR = new;
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initial begin
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  accum = new;    // Create a new Register object; its handle is in accum
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  accum.data = 8'h1f;        // Store value in data member
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  $display("accum.data = %0h", accum.data);
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  accum.load(8'h1f);         // A better way of doing it
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  $display("accum.data = %0h", accum.data);
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end
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initial begin
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  static Register accum1 = new;        // Alternative
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  static Register accum2 = new(8'hff); // Initialize
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  static Register accum3[10];
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  foreach (accum3[i])
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    accum3[i] = new;    // Array of 10 Registers
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end
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initial begin
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  SR.load(8'h55);                      // Inherited method
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  $display("SR.data = %0h", SR.data);
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  SR.shiftleft;                        // data now has 8’aa
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  $display("SR.data = %0h (after shift left)", SR.data);
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end
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endmodule
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// Code your design here
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A complete SystemVerilog example for class topic.

A complete SystemVerilog example for class topic.

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