DOULOS EASIER UVM CODE GENERATOR
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By clicking on the Enable Easier UVM checkbox, you have enabled access to the Doulos Easier UVM Code Generator. The Easier UVM Code Generator enables you to generate UVM testbenches from simple control files and snippets of SystemVerilog code.
The control files specify the testbench. You will always need at least three control files:
- a Common Template File, which is the master file for code generation,
- at least one Interface Template File, one per interface, and
- a pinlist file, which specifies which DUT pins are connected to which interface variables.
The snippets of SystemVerilog code allow you to customize the test bench to your specific requirements, e.g. to drive the pins of each interface to the design under test (DUT).
To get started, take a look at the examples listed in the Examples section on the left of the EDA Playground window. You can access the full set of reference documentation, tutorials, and videos by clicking on the blue i next to the Enable Easier UVM checkbox.
You can download the generated code by clicking on the Download files after run checkbox.
Easier UVM on EDA Playground is a great way to get started with UVM: you can generate and run working UVM testbench code quickly and easily on EDA Playground. Alternatively, you can download the Easier UVM Code Generator to run on your own computer by clicking on the blue i next to the Enable Easier UVM checkbox.
DIFFERENCES WHEN RUNNING THE CODE GENERATOR IN EDA PLAYGROUND
To get the Easier UVM Code Generator working in EDA Playground, we have had to make some changes. If you already use the Easier UVM Code Generator, here are some things you need to know:
- Template files, the pinlist file, include files and any regmodel file have to be created as EDA Playground testbench tabs (on the left)
- DUT files have to be created as EDA Playground design tabs (on the right)
- Template files must have the file extension .tpl, include files and DUT files must have the file extension .sv
- The default design tab is named design.sv. This tab may contain DUT code or may be empty. Either way, you may add further design tabs.
- Optionally, you can add an EDA Playground design tab named files.f that lists the other design tabs/files in the order they are to be compiled. If absent, all the design tabs will be compiled in alphabetical order.
- It is not possible to pass command line arguments to the generator script, so the Common Template File must be named common.tpl, and the only way to specify a prefix is using the prefix setting in common.tpl
- The dut_source_path and inc_path settings in common.tpl are unnecessary in EDA Playground (because the files are created as tabs and identified from their file extensions). If the settings are present, their values do not affect the generated code.
- The dut_pfile setting in common.tpl must not include a hierarchical directory path (because the pinlist file is created as a tab). The default is dut_pfile = pinlist.
