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testbench.sv

 
module Test (input bit[7:0] Addr, Data);
​
  initial
    #100 $stop;
​
endmodule
​
​
module CheckAddr (input clk, bit[7:0] Addr, Max);
  default clocking cb @(posedge clk); endclocking
    A1: assert property (Addr <= Max)
        else $error("Address is out of range");
endmodule
​
      
module DUT_TB;
  bit[7:0] Addr, Data;
  bit clk;
​
  assign #5 clk = (clk == 1'b1 ? 1'b0 : 1'b1);
  assign #10 Addr = Addr + 1;
  
  DUT dut_inst (clk, Addr, Data);
​
  // Binds an instance of the module Test to the testbench
  bind DUT_TB Test Test_inst(Addr, Data);
​
  // Binds an instance of the module CheckAddr to the DUT instance
  bind DUT_TB.dut_inst CheckAddr CA_inst1(clk, Addr, Data);
​
  // Alternative syntax for the above
  bind DUT: dut_inst CheckAddr CA_inst2(clk, Addr, Data);
​
​
  // Dump waves
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(1, DUT_TB.dut_inst);
  end
  
endmodule

design.sv

xxxxxxxxxx
 
module DUT (input clk, bit[7:0] Addr,
            output     bit[7:0] Data);
​
  always @(posedge clk)
  begin
    Data = Addr + 1;
  end
​
endmodule

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