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EDA Playground lets you type in and run HDL code (using a selection of free and commercial simulators and synthesizers).
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UVM / OVM

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Examples

using EDA Playground
VHDL
Verilog/SystemVerilog
UVM
EasierUVM
SVAUnit
SVUnit
VUnit (Verilog/SV)
VUnit (VHDL)
TL-Verilog
e + Verilog
Python + Verilog
Python Only
C++/SystemC

208

testbench.sv

 
// Code your testbench here
// or browse Examples
​
module digital_clock_tb;
  
  reg clk = 1'b0;
  
  always #10 clk = ~clk;
  
  digital_clock digital_clock0 (.clk(clk));
  
  initial #100000 $finish;
  
  always begin 
    #10000 $display("tick");
    #10000 $display("tock");
  end
  
  initial begin
    $dumpfile("dump.vcd"); $dumpvars;
  end
                           
endmodule
​

design.sv

xxxxxxxxxx
 
// Code your design here
​
module digital_clock(input clk);
​
localparam N = 26;
reg [N-1:0] slow_clk = 0;
reg [7:0] countsec = 0;
  
wire enable;
​
always @ (posedge clk)
  if (slow_clk == 26'd49) slow_clk <= 8'b0;
    else  slow_clk <= slow_clk + 8'b1;
​
assign enable = (slow_clk == 26'd49);
​
always @ (posedge clk)
  if (enable == 1'b1)
    if (countsec == 8'b00111011) countsec <= 8'b0;
    else  countsec <= countsec + 8'b1;
​
endmodule

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