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using EDA Playground
VHDL
Verilog/SystemVerilog
UVM
EasierUVM
SVAUnit
SVUnit
VUnit (Verilog/SV)
VUnit (VHDL)
TL-Verilog
e + Verilog
Python + Verilog
Python Only
C++/SystemC

203

 
// Code your testbench here
​
interface some_interface();
  bit clk;
  logic some_signal;
endinterface
​
​
package some_package;
  
  class some_master_class;
    virtual some_interface vif;
    
    task do_something();
      @(posedge vif.clk);
      vif.some_signal <= 1;
      
      @(posedge vif.clk);
      vif.some_signal <= 0;
​
      @(posedge vif.clk);
    endtask
  endclass
    
endpackage
​
​
module top;
​
  import some_package::*;
​
  some_interface my_if();
  
  bit clk, some_signal;
  always #1 clk = ~clk;
  
  assign my_if.clk = clk;
  assign my_if.some_signal = some_signal;
​
​
  initial begin
    some_master_class master = new();    
    master.vif = my_if;
    
    master.do_something();
    
    $finish();
  end
​
endmodule
​

design.sv

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// Code your design here
​

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